HT32F57341仿真时出现这个，编译无错

只看该作者 · 2021-3-17 13:55

Load "C:\\Users\\hppen\\Desktop\\HT32Fxx\\example\\GPIO\\InputOutput\\MDK_ARMv5\\Obj\\HT32.axf"
Cannot access Memory (@ 0x00000000, Write, Acc Size: 4 Byte)
Cannot access Memory (@ 0x00001000, Write, Acc Size: 4 Byte)
*** error 57: illegal address (0x00001000)
Include "C:\\Users\\hppen\\Desktop\\HT32Fxx\\example\\GPIO\\InputOutput\\MDK_ARMv5\\HT32F5xxxx_01_DebugSupport.ini"
/*----------------------------------------------------------------------------------------------------------*/
/* Holtek Semiconductor Inc. */
/* */
/* Copyright (C) Holtek Semiconductor Inc. */
/* All rights reserved. */
/* */
/*------------------------------------------------------------------------------------------------------------
 File Name : HT32F5xxxx_01_DebugSupport.ini
 Version : V1.03
 Date : 2019-07-08
 Description : Debug Support Initialization file.
------------------------------------------------------------------------------------------------------------*/

// Supported Device
// ========================================
// HT32F5xxxx

// <<< Use Configuration Wizard in Context Menu >>>
FUNC void DebugSupport (void)
{

// <e0.0> Configure MCU Debug Control Register
// <o2.0> Debug Sleep Mode (DBSLP)
// LDO = On, FCLK = On, and HCLK = On in Sleep mode
// <o2.1> Debug Deep-Sleep Mode 1 (DBDSLP1)
// LDO = On, FCLK = On, and HCLK = On in Deep-Sleep mode 1
// <o2.14> Debug Deep-Sleep Mode 2 (DBDSLP2)
// LDO = On, FCLK = On, and HCLK = On in Deep-Sleep mode 2
// <o2.2> Debug Power-Down Mode (DBPD)
// LDO = On, FCLK = On, and HCLK = On in Power-Down mode
// <o2.3> WDT Debug Mode Enable (DBWDT)
// WDT Timer counter is stopped when the core is halted
// <o2.4> MCTM0 Debug Mode Enable (DBMCTM0)
// MCTM0 Timer counter is stopped when the core is halted
// <o2.6> GPTM0 Debug Mode Enable (DBGPTM0)
// GPTM0 Timer counter is stopped when the core is halted
// <o2.7> GPTM1 Debug Mode Enable (DBGPTM1)
// GPTM1 Timer counter is stopped when the core is halted
// <o2.8> USART0 Debug Mode Enable (DBUSART0)
// USART0 Rx FIFO timeout counter is stopped when the core is halted
// <o2.9> USART1 Debug Mode Enable (DBUSART1)
// USART1 Rx FIFO timeout counter is stopped when the core is halted
// <o2.18> UART0 Debug Mode Enable (DBUART0)
// UART0 Rx FIFO timeout counter is stopped when the core is halted
// <o2.19> UART1 Debug Mode Enable (DBUART1)
// UART1 Rx FIFO timeout counter is stopped when the core is halted
// <o2.26> UART2 Debug Mode Enable (DBUART2)
// UART2 Rx FIFO timeout counter is stopped when the core is halted
// <o2.27> UART3 Debug Mode Enable (DBUART3)
// UART3 Rx FIFO timeout counter is stopped when the core is halted
// <o2.10> SPI0 Debug Mode Enable (DBSPI0)
// SPI0 Rx FIFO timeout counter is stopped when the core is halted
// <o2.11> SPI1 Debug Mode Enable (DBSPI1)
// SPI1 Rx FIFO timeout counter is stopped when the core is halted
// <o2.12> I2C0 Debug Mode Enable (DBI2C0)
// I2C0 timeout counter is stopped when the core is halted
// <o2.13> I2C1 Debug Mode Enable (DBI2C1)
// I2C1 timeout counter is stopped when the core is halted
// <o2.28> I2C2 Debug Mode Enable (DBI2C2)
// I2C2 timeout counter is stopped when the core is halted
// <o2.15> SCI0 Debug Mode Enable (DBSCI0)
// SCI0 Waiting Time counter is stopped when the core is halted
// <o2.21> SCI1 Debug Mode Enable (DBSCI1)
// SCI1 Waiting Time counter is stopped when the core is halted
// <o2.16> BFTM0 Debug Mode Enable (DBBFTM0)
// BFTM0 Timer counter is stopped when the core is halted
// <o2.17> BFTM1 Debug Mode Enable (DBBFTM1)
// BFTM1 Timer counter is stopped when the core is halted
// <o2.22> SCTM0 Debug Mode Enable (DBSCTM0)
// SCTM0 Timer counter is stopped when the core is halted
// <o2.23> SCTM1 Debug Mode Enable (DBSCTM1)
// SCTM1 Timer counter is stopped when the core is halted
// <o2.24> SCTM2 Debug Mode Enable (DBSCTM2)
// SCTM2 Timer counter is stopped when the core is halted
// <o2.25> SCTM3 Debug Mode Enable (DBSCTM3)
// SCTM3 Timer counter is stopped when the core is halted
// <o2.30> PWM0 Debug Mode Enable (DBPWM0)
// PWM0 counter is stopped when the core is halted
// <o2.31> PWM1 Debug Mode Enable (DBPWM1)
// PWM1 counter is stopped when the core is halted
// </e>
 if (0)
 {
_WDWORD(0x40088304, 0x00000000);
 }
}

DebugSupport();

/*----------------------------------------------------------------------------------------------------------*/
/* Uncomment to debug stack/heap underflow, overflow, and overwrite */
/*----------------------------------------------------------------------------------------------------------*/
//BS Write __HT_check_sp, 2
//BS Write __HT_check_heap, 2

/*----------------------------------------------------------------------------------------------------------*/
/* Load debug symbol */
/*----------------------------------------------------------------------------------------------------------*/
//LOAD %L INCREMENTAL

HT32F57341仿真时出现这个，编译无错

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