上程序了，下面这段是我自己写的一段锁存器程序，编译时没有出错，然后把它放到原理图上编译就出现了上面的问题，请大家看看有什么问题。。
module lock(syclk,test,in1,in2,in3,in4,in5,in6,in7,in8,out1,out2,out3,out4,out5,out6,out7,out8);
input syclk,test,in1,in2,in3,in4,in5,in6,in7,in8;
output reg out1,out2,out3,out4,out5,out6,out7,out8;
reg [31:0] cnt;
reg register1,register2,register3,register4,register5,register6,register7,register8;
always @(posedge syclk or negedge test)
begin
if(~test)
register1<=in1;
register2<=in2;
register3<=in3;
register4<=in4;
register5<=in5;
register6<=in6;
register7<=in7;
register8<=in8;
//delay function
begin
if(cnt!=0)
cnt<=cnt-1'b1;
else
cnt<=32'b1001_1000_1001_0110_1000_0000;//delay about 200ms
end
if(test)
begin
out1<=register1;
out2<=register2;
out3<=register3;
out4<=register4;
out5<=register5;
out6<=register6;
out7<=register7;
out8<=register8;
end
end
endmodule |
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