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【求助】请教一下各位大神GD32F450移植sram问题

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yllyylly6666|  楼主 | 2021-8-26 09:23 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
本人把EXMC里面的psram的相关代码从stm32f427移植到GD32F450的过程出现问题,初始化以后内存地址里是有规律的乱码,写数后立刻被覆盖。官方demo里面只有NAND和sdram,没有norram相关的。修改的初始化代码如下。注释的是原来stm32的,感觉都对应的很好。不知道有没有大神有这方面的经验,谢谢
// FMC Configuration
       
          p.asyn_address_setuptime = 2;
          p.asyn_address_holdtime = 1;
          p.asyn_data_setuptime = 2;
          p.bus_latency = 1;
          p.syn_clk_division =0;
          p.syn_data_latency = 0;
          p.asyn_access_mode = EXMC_ACCESS_MODE_A;
       
//          p.FMC_AddressSetupTime = 2;
//          p.FMC_AddressHoldTime = 1;
//          p.FMC_DataSetupTime = 2;
//          p.FMC_BusTurnAroundDuration = 1;
//          p.FMC_CLKDivision = 0;
//          p.FMC_DataLatency = 0;
//          p.FMC_AccessMode = FMC_AccessMode_A;
        //
        //exmc_norsram_deinit(EXMC_BANK0_NORSRAM_REGION2);

       
       
        FMC_NORSRAMInitStructure.norsram_region = EXMC_BANK0_NORSRAM_REGION2;
          FMC_NORSRAMInitStructure.address_data_mux = DISABLE;
          FMC_NORSRAMInitStructure.memory_type = EXMC_MEMORY_TYPE_PSRAM;
          FMC_NORSRAMInitStructure.databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
          FMC_NORSRAMInitStructure.burst_mode = DISABLE;
          FMC_NORSRAMInitStructure.asyn_wait = DISABLE;  
          FMC_NORSRAMInitStructure.nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
          FMC_NORSRAMInitStructure.wrap_burst_mode = DISABLE;
          FMC_NORSRAMInitStructure.nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
          FMC_NORSRAMInitStructure.memory_write = ENABLE;
          FMC_NORSRAMInitStructure.nwait_signal = DISABLE;
          FMC_NORSRAMInitStructure.extended_mode = DISABLE;
//  FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
        FMC_NORSRAMInitStructure.write_mode = EXMC_ASYN_WRITE;//不可以用EXMC_SYN_WRITE
          FMC_NORSRAMInitStructure.read_write_timing = &p;
          FMC_NORSRAMInitStructure.write_timing = &p;
       
//          FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM3;
//          FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
//          FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_PSRAM;
//          FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b;
//          FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
//          FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;  
//          FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
//          FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
//          FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
//          FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
//          FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
//          FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
//          FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
//        FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
//          FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &p;
//          FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &p;
          exmc_norsram_init(&FMC_NORSRAMInitStructure);
        exmc_norsram_consecutive_clock_config(EXMC_CLOCK_SYN_MODE);
          exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION2);//FMC_NORSRAMCmd(FMC_Bank1_NORSRAM3, ENABLE);       

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