大家好,小弟刚刚入手fpga。有些小问题我实在是弄不明白,各位高手可能看一眼就知道问题……请各位高手帮忙看看,小弟不胜感激。就是线面红色的clk为什么不可以用num替换呢,num作为敏感信号为什么显示的就是乱码啊,仿真输出都是x不确定。
module DISPLAY(clk,wela,dula);
input clk;
output wela; output [6:0]dula;
assign wela=1;
parameter code0=7'h3f, //display code(Cathode)
code1=7'h06,
code2=7'h5b,
code3=7'h4f,
code4=7'h66,
code5=7'h6d,
code6=7'h7d,
code7=7'h07,
code8=7'h7f,
code9=7'h6f,
code10=7'h77,
code11=7'h7c,
code12=7'h39,
code13=7'h5e,
code14=7'h79,
code15=7'h71;
reg [22:0]num;
[email=always@(posedge]always@(posedge[/email] clk)
begin
num<=num+1'b1;
end
reg[3:0]data;
[email=always@(posedge]always@(posedge[/email] clk) //why ""posedge clk"" con't be replaced by ""num""?
begin
if(num==4'h7fffff)data<=data+1'b1; //role play a delay
end
reg [6:0]dula;
[email=always@(data]always@(data[/email])
case(data)
0:dula<=code0;
1:dula<=code1;
2:dula<=code2;
3:dula<=code3;
4:dula<=code4;
5:dula<=code5;
6:dula<=code6;
7:dula<=code7;
8:dula<=code8;
9:dula<=code9;
10:dula<=code10;
11:dula<=code11;
12:dula<=code12;
13:dula<=code13;
14:dula<=code14;
15:dula<=code15;
default: ;
endcase
endmodule |