module fen(clk, kind, key, seg_bit, seg_dat, ext_sig, out);
input kind;
input [4:0] key;
input clk;
input ext_sig;
output reg [2:0]seg_bit;
output reg [7:0]seg_dat;
output reg out;
reg [7:0] dis_code[10:0];
reg [31:0] timer=0;
reg [3:0] dis_ram2, dis_ram1, dis_ram0;
reg [3:0] dis_bit=0;
reg [3:0] i=0, j=0, k=0;
reg b_but_en=0;
reg [15:0] counter=0;
reg b_f=0, b_ff=0;
reg [3:0]c_ff=0;
initial
begin
dis_code[0]= 'b00111111;
dis_code[1]= 'b00000110;
dis_code[2]= 'b01011011;
dis_code[3]= 'b01001111;
dis_code[4]= 'b01100110;
dis_code[5]= 'b01101101;
dis_code[6]= 'b01111101;
dis_code[7]= 'b00000111;
dis_code[8]= 'b01111111;
dis_code[9]= 'b01101111;
dis_code[10]= 'b01000000;
dis_ram0 = 1;
dis_ram1 = 0;
dis_ram2 = 4;
i=0;
j=0;
k=0;
end
always @(posedge timer[20]) // key scan and deal
begin
if(key=='h1f) b_but_en = 1;
else if(b_but_en)
begin
b_but_en=0;
if(!key[0]) //
begin dis_ram0=dis_ram0+1; if(dis_ram0>=dis_ram2) dis_ram0=1; end
else if(!key[1]) //
begin dis_ram2=dis_ram2+1; if(dis_ram2>=10) dis_ram2=2; end
else if(!key[2]) //
begin dis_ram2=dis_ram2-1; if(dis_ram2==1) dis_ram2=9; end
else if(!key[3])
begin dis_ram1=dis_ram1+1; if(dis_ram1>=10) dis_ram1=0; end
else if(!key[4])
begin dis_ram1=dis_ram1-1; if(dis_ram1==15) dis_ram1=9; end
if ((dis_ram1!=0)||(dis_ram2==1)) dis_ram0=10;
else if(dis_ram0==10) dis_ram0=1;
end
end
always @(posedge timer[15])
begin
dis_bit = dis_bit+1;
dis_bit = dis_bit%3;
seg_bit = (~(1<<(dis_bit)));
if(dis_bit==0)
seg_dat = (~dis_code[dis_ram0]);
else if(dis_bit==1)
seg_dat = (~dis_code[dis_ram1]);
else if(dis_bit==2)
seg_dat = (~dis_code[dis_ram2]);
if(dis_bit==2) seg_dat[7]=0;
end
always@ (posedge clk)
begin
timer = timer+1;
end
always@ (posedge ext_sig)
//always@ (posedge b_ff)
//always@ ( posedge ext_sig or negedge ext_sig )
begin
counter = counter+1;
///out = counter[0];
if(dis_ram1==0)
begin
if(counter%(dis_ram2)==0) out=1;
else if(counter%(dis_ram2)==dis_ram0) out=0;
end
else
begin
// N.X?? (10-X)?N???X?(N+1)???
if(dis_ram2%2==0)
begin
if(i>0)
begin
if(counter>=(dis_ram2)) begin out=1; i=i-1; counter=0; end
else if(counter==(dis_ram2/2)) begin out=0; i=i-1; end
end
else if(j>0)
begin
if(counter>=(dis_ram2+1)) begin out=1; j=j-1; counter=0; end
else if(counter==(dis_ram2/2)) begin out=0; j=j-1; end
if(j==0)
begin
i=(10-dis_ram1)*2;
j=dis_ram1*2;
end
end
else
begin
i=(10-dis_ram1)*2;
j=dis_ram1*2;
end
end
else
begin
if(i>0)
begin
if(counter>=(dis_ram2)) begin out=1; i=i-1; counter=0; end
else if(counter==((dis_ram2-1)/2)) begin out=0; i=i-1; end
end
else if(j>0)
begin
if(counter>=(dis_ram2+1)) begin out=1; j=j-1; counter=0; end
else if(counter==((dis_ram2+1)/2)) begin out=0; j=j-1; end
if(j==0)
begin
i=(10-dis_ram1)*2;
j=dis_ram1*2;
end
end
else
begin
i=(10-dis_ram1)*2;
j=dis_ram1*2;
end
end
end
end
endmodule |
楼主
标题置顶
标题高亮
