华大HC32F460系列搭建FreeRTOS记录

HC32F46x,USE_DEVICE_DRIVER_LIB,ARM_MATH_CM4

#define configUSE_PREEMPTION                        1

#define configUSE_IDLE_HOOK                                0

#define configUSE_TICK_HOOK                                0

#define configCPU_CLOCK_HZ                                ( SystemCoreClock )

#define configTICK_RATE_HZ                                ( ( TickType_t ) 10*1000 )   //200,000k/10k = 20,000k

#define configMAX_PRIORITIES                        ( 5 )

#define configMINIMAL_STACK_SIZE                ( ( unsigned short ) 130 )

#define configTOTAL_HEAP_SIZE                        ( ( size_t ) ( 75 * 1024 ) )

#define configMAX_TASK_NAME_LEN                        ( 10 )

#define configUSE_TRACE_FACILITY                1

#define configUSE_16_BIT_TICKS                        0

#define configIDLE_SHOULD_YIELD                        1

#define configUSE_MUTEXES                                1

#define configQUEUE_REGISTRY_SIZE                8

#define configCHECK_FOR_STACK_OVERFLOW  0

#define configUSE_RECURSIVE_MUTEXES                1

#define configUSE_MALLOC_FAILED_HOOK        0

#define configUSE_APPLICATION_TASK_TAG        1

#define configUSE_COUNTING_SEMAPHORES        1

#define configGENERATE_RUN_TIME_STATS        0

/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS

standard names. */

#define vPortSVCHandler SVC_Handler//SVC_IrqHandler

#define xPortPendSVHandler PendSV_Handler//PendSV_IrqHandler

#define xPortSysTickHandler SysTick_Handler//SysTick_IrqHandler

/**

 *******************************************************************************

 ** \brief  The system clock source.

 **

 ******************************************************************************/

 typedef enum en_clk_sys_source

 {

     ClkSysSrcHRC                   = 0u,   ///< The system clock source is HRC.

     ClkSysSrcMRC                   = 1u,   ///< The system clock source is MRC.

     ClkSysSrcLRC                   = 2u,   ///< The system clock source is LRC.

     ClkSysSrcXTAL                  = 3u,   ///< The system clock source is XTAL.

     ClkSysSrcXTAL32                = 4u,   ///< The system clock source is XTAL32.

     CLKSysSrcMPLL                  = 5u,   ///< The system clock source is MPLL.

 }en_clk_sys_source_t;