SCU_MCLKSourceConfig(SCU_MCLK_OSC);
// Set the PLL's multipliers and dividers
SCU_PLLFactorsConfig(60, BSP_PLL_M, BSP_PLL_P); //30Mhz clock
SCU_PLLCmd(ENABLE); // Enable the PLL
SCU_RCLKDivisorConfig(SCU_RCLK_Div1); // Set RCLK, the CPU clock's main divider
SCU_PCLKDivisorConfig(SCU_PCLK_Div1); // Set APBDIV, the PCLK divider
SCU_FMICLKDivisorConfig(SCU_FMICLK_Div2);
SCU_MCLKSourceConfig(SCU_MCLK_PLL); // Select the PLL output as CPU clock