请教关于3段式状态机的问题

只看该作者 · 2012-3-21 15:51

本帖最后由 alecsoo 于 2012-3-21 15:59 编辑

关于3段式状态机的问题，请各位大虾指教：
代码：
reg [1:0] state_now=2'b00;  // 表示系统当前状态
reg [1:0] state_next=2'b00;  // 表示系统下一个状态

parameter
      Wait = 2'b00,  // 等待状态
   Send = 2'b01; // 产生发送

always @(posedge clk or posedge rst) begin
   if(rst) begin
            state_now <= Wait;
   end
   else begin
         state_now <= state_next;
   end
end

always @(state_now or start or type) begin
   case(state_now)
            Wait:
               if(start) begin
                     state_next = Send;
                     case(type)
                           2'b00: duty<=1;
                           2'b01: duty<=5;
                           2'b10: duty<=9;
                        2'b11: duty<=0;
                     endcase
            end
         Send:
               if(!start) begin
                     state_next = Wait;
                     duty<=0;
               end
         endcase
   end

always @(posedge clk or  posedge rst) begin
      if(rst)
         dout <= 1'b0;
      else
      case(state_next)
            Wait:;
            Send:;
            default：;
      endcase
end

为什么编译后总是有warning：
WARNING:Xst:737 - Found 2-bit latch for signal <state_next>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <state_next_0> of sequential type is unconnected in block <;PrintHclk>.
WARNING:Xst:2677 - Node <state_next_1> of sequential type is unconnected in block <;PrintHclk>.
WARNING:Xst:2677 - Node <state_now_1> of sequential type is unconnected in block <;PrintHclk>.
WARNING:Xst:2677 - Node <state_now_0> of sequential type is unconnected in block <;PrintHclk>.

请高人指点！

只看该作者 · 2012-3-21 16:08

1# alecsoo 如图所示，没有default。

只看该作者 · 2012-3-21 16:19

2# bityoung

首先谢谢 bityoung的指导

两个语句中都将default加上了
但是还是提示：
WARNING:Xst:737 - Found 2-bit latch for signal <state_next>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <duty>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.