always @(posedge clk or posedge rst) begin
if(rst) begin
state_now <= Wait;
end
else begin
state_now <= state_next;
end
end
always @(state_now or start or type) begin
case(state_now)
Wait:
if(start) begin
state_next = Send;
case(type)
2'b00: duty<=1;
2'b01: duty<=5;
2'b10: duty<=9;
2'b11: duty<=0;
endcase
end
Send:
if(!start) begin
state_next = Wait;
duty<=0;
end
endcase
end
always @(posedge clk or posedge rst) begin
if(rst)
dout <= 1'b0;
else
case(state_next)
Wait:;
Send:;
default：;
endcase
end
为什么编译后总是有warning：
WARNING:Xst:737 - Found 2-bit latch for signal <state_next>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <state_next_0> of sequential type is unconnected in block <;PrintHclk>.
WARNING:Xst:2677 - Node <state_next_1> of sequential type is unconnected in block <;PrintHclk>.
WARNING:Xst:2677 - Node <state_now_1> of sequential type is unconnected in block <;PrintHclk>.
WARNING:Xst:2677 - Node <state_now_0> of sequential type is unconnected in block <;PrintHclk>.
两个语句中都将default加上了
但是还是提示：
WARNING:Xst:737 - Found 2-bit latch for signal <state_next>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <duty>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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