[ARM入门] STM32F030启用内部晶振

static void SetSysClock(void)



{



if (HSEStatus == (uint32_t)0x01) // 存在外部时钟

{

}

else

{

// 这里添加配置48M代码

}

}

static void SetSysClock(void)

{

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;



  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/

  /* Enable HSE */

  RCC->CR |= ((uint32_t)RCC_CR_HSEON);



  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));



  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }



  if (HSEStatus == (uint32_t)0x01) // 存在外部时钟

  {

    /* Enable Prefetch Buffer and set Flash Latency */

    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;



    /* HCLK = SYSCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;



    /* PCLK = HCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;



    /* PLL configuration = HSE * 6 = 48 MHz */

    RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);



    /* Enable PLL */

    RCC->CR |= RCC_CR_PLLON;



    /* Wait till PLL is ready */

    while ((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }



    /* Select PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));

    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;



    /* Wait till PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)

    {

    }

  }

  else

  {

    // HSI 内部时钟做为PLL时钟源并配置PLL 48M做为系统时钟

    /* Enable Prefetch Buffer and set Flash Latency */

    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;



    /* HCLK = SYSCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;



    /* PCLK = HCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;



    // PLL configuration = (HSI/2) * 12 = 48 MHz

    RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_12); // 8M/2 * 12 = 48M



    /* Enable PLL */

    RCC->CR |= RCC_CR_PLLON;



    /* Wait till PLL is ready */

    while ((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }



    /* Select PLL as system clock source */

    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); // PLL 做系统时钟



    /* Wait till PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)

    {

    }

  }

}