本帖最后由 shgij123 于 2022-7-20 00:44 编辑
环境:Quartus13.1+modelsim2020.4
问题:使用rtl联合仿真,成功启动modelsim但是波形有问题,所有输入输出端的值均为'x'
源代码:
`timescale 1ns/1ns
module decoder_38(
input E1_n ,
input E2_n ,
input E3 ,
/* 三个使能输入端E1、E2、E3,
E1高电平有效,E2\E3低电平有效
三个信号均为有效时输出端才输出正确信号
*/
input A0 ,
input A1 ,
input A2 ,
/*三个数据输入端,序号越大权值越大,高电平有效*/
output wire Y0_n ,
output wire Y1_n ,
output wire Y2_n ,
output wire Y3_n ,
output wire Y4_n ,
output wire Y5_n ,
output wire Y6_n ,
output wire Y7_n
/*数据输出端,权值排列同输入端,高电平有效*/
);
reg Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r;
always@(*) begin
casez({E3, E2_n, E1_n, A2, A1, A0})
6'bx1x_xxx: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0000;
6'bxx1_xxx: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0000;
6'b0xx_xxx: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0000;
6'b100_000: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b1000_0000;
6'b100_001: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0100_0000;
6'b100_010: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0010_0000;
6'b100_011: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0001_0000;
6'b100_100: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_1000;
6'b100_101: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0100;
6'b100_110: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0010;
6'b100_111: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0001;
default: {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r} = 8'b0000_0000;
endcase
end
assign {Y0_n, Y1_n, Y2_n, Y3_n, Y4_n, Y5_n, Y6_n, Y7_n} = {Y0_r, Y1_r, Y2_r, Y3_r, Y4_r, Y5_r, Y6_r, Y7_r};
endmodule
测试平台:`timescale 1 ns/ 1 ns
module decoder_38_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg A0;
reg A1;
reg A2;
reg E1_n;
reg E2_n;
reg E3;
// wires
wire Y0_n;
wire Y1_n;
wire Y2_n;
wire Y3_n;
wire Y4_n;
wire Y5_n;
wire Y6_n;
wire Y7_n;
// assign statements (if any)
decoder_38 i1 (
// port map - connection between master ports and signals/registers
.A0(A0),
.A1(A1),
.A2(A2),
.E1_n(E1_n),
.E2_n(E2_n),
.E3(E3),
.Y0_n(Y0_n),
.Y1_n(Y1_n),
.Y2_n(Y2_n),
.Y3_n(Y3_n),
.Y4_n(Y4_n),
.Y5_n(Y5_n),
.Y6_n(Y6_n),
.Y7_n(Y7_n)
);
initial
begin
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'bx1x_xxx;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'bxx1_xxx;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b0xx_xxx;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_000;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_001;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_010;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_011;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_100;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_101;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_110;
#100 {E3,E2_n,E1_n,A2,A1,A0}=6'b100_111;
#200 $stop;
end
endmodule
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