我有一块CPLD板子,自己写了个闪灯程序不对。听特权同学的视频教程,写了个test bench仿真程序。
可是仿真出现问题。
CPLD代码:
module LAMP(input clk,input rst_n,output led4);
reg[5:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n) cnt<=6'd0;
else if(cnt<6'd49) cnt<=cnt+1'b1;
else cnt<=6'd0;
assign led4=(cnt <= 6'd24) ? 1'b0 : 1'b1;
endmodule
test bench文件:
`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led4;
// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led4(led4),
.rst_n(rst_n)
);
initial
begin
clk=0;
forever
#10 clk=~clk
// code that executes only once
// insert code here --> begin
// --> end
$display("Running testbench");
end
initial begin
rst_n=0;
#1000;
rst_n=1;
#5000;
$stop
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
仿真出现的问题现象是Hierarchy view not support
仿真软件版本是Modelsim SE-64 10.4
图片传不上去,不知为何。谢谢!
|