我的testbench仿真文件如下:
`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led;
// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led),
.rst_n(rst_n)
);
reg [7:0] memory [0:255];
integer scan;
integer index=3;
initial begin
clk=0;
#10 clk=~clk;
end
initial begin
$readmemh("memory.list", memory);
end
if(index>0)
begin
for(scan=0;scan<index;scan=scan+1)
if(memory[scan]>0)
begin
$display("%d",memory[scan]);
end
end
else
$display("error--indexiszero");
endmodule
可是运行仿真出错,提示:
请高手解惑,谢谢!
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