我仿真夏宇闻老师书上的例子
代码如下：
`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
wire b;
reg clk;
wire d;
reg rst_n;
// wires
wire a;
wire c;
// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.a(a),
.b(b),
.c(c),
.clk(clk),
.d(d),
.rst_n(rst_n)
);
always @(posedge clk)
begin
a=b;
c=d;
end
always @(posedge clk)
$strobe("Displaying a=%b,c=%b",a,c);
endmodule
其实就是
a=b;
c=d;那两条语句出错。
高手支招，谢谢！
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