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HC32F460芯片EVT触发ADC转换,使用timer peak不能成功,使用UP可以

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17688775540|  楼主 | 2022-10-19 10:23 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
HC32F460芯片的Timer4 EVT触发ADC转换,为什么使用peak一直不能成功,而使用UP就可以触发转换,但是发现每个定时器周期触发了两次ADC转换  

////////////定时器部分
stc_tmr4_init_t stcTmr4Init;
    stc_tmr4_oc_init_t stcTmr4OcInit;
    un_tmr4_oc_ocmrh_t unTmr4OcOcmrh;
    un_tmr4_oc_ocmrl_t unTmr4OcOcmrl;
    stc_tmr4_pwm_init_t stcTmr4PwmInit;
    stc_tmr4_evt_init_t stcTmr4EventInit;

    /* Enable TMR4_2 peripheral clock */
    FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4_2, ENABLE);

    /************************* Configure TMR4_2 counter *************************/
    stcTmr4Init.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK;
    stcTmr4Init.u16ClockDiv = TMR4_CLK_DIV1;
    stcTmr4Init.u16CountMode = TMR4_MD_TRIANGLE;
    stcTmr4Init.u16PeriodValue = 2500;
    (void)TMR4_Init(CM_TMR4_2, &stcTmr4Init);

    /* Enable TMR4_2 peak interrupt */
    TMR4_IntCmd(CM_TMR4_2, TMR4_INT_CNT_PEAK, ENABLE);

    /************************* Configure TMR4_2_VL output-compare ******************/
    /* Initialize TMR4_2_VL OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_2_VL OC channel initialize */
    stcTmr4OcInit.u16CompareValue = 1250;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_2, TMR4_OC_CH_VL, &stcTmr4OcInit);

    /* TMR4_2_VL OC channel: compare mode OCMR */
    unTmr4OcOcmrl.OCMRx = (uint32_t)0x0;
    TMR4_OC_SetLowChCompareMode(CM_TMR4_2, TMR4_OC_CH_VL, unTmr4OcOcmrl);

    /* TMR4_2_VL OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_2, TMR4_OC_CH_VL, ENABLE);

    /************************* Configure TMR4_2_WH output-compare ******************/
    /* Initialize TMR4_2_WH OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_2_WH OC channel initialize */
    stcTmr4OcInit.u16CompareValue = 1250;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_2, TMR4_OC_CH_WH, &stcTmr4OcInit);

    /* TMR4_2_WH OC channel: compare mode OCMR */
    unTmr4OcOcmrh.OCMRx = (uint16_t)0x0;
    TMR4_OC_SetHighChCompareMode(CM_TMR4_2, TMR4_OC_CH_WH, unTmr4OcOcmrh);

    /* TMR4_2_WH OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_2, TMR4_OC_CH_WH, ENABLE);

    /************************* Configure TMR4_2_WL output-compare ******************/
    /* Initialize TMR4_2_WL OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_2_WL OC channel initialize */
    stcTmr4OcInit.u16CompareValue = 1250;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_2, TMR4_OC_CH_WL, &stcTmr4OcInit);

    /* TMR4_2_WL OC channel: compare mode OCMR */
    unTmr4OcOcmrl.OCMRx = (uint32_t)0x0;
    TMR4_OC_SetLowChCompareMode(CM_TMR4_2, TMR4_OC_CH_WL, unTmr4OcOcmrl);

    /* TMR4_2_WL OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_2, TMR4_OC_CH_WL, ENABLE);

    /************************* Configure TMR4_2_V PWM *****************************/
    /* TMR4_2_V PWM: initialize */
    (void)TMR4_PWM_StructInit(&stcTmr4PwmInit);
    stcTmr4PwmInit.u16Mode = TMR4_PWM_MD_DEAD_TMR;
    stcTmr4PwmInit.u16ClockDiv = TMR4_PWM_CLK_DIV1;
    stcTmr4PwmInit.u16Polarity = TMR4_PWM_OXH_INVT_OXL_INVT;
    (void)TMR4_PWM_Init(CM_TMR4_2, TMR4_PWM_CH_V, &stcTmr4PwmInit);

    /* TMR4_2_V PWM: set dead time count */
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_2, TMR4_PWM_CH_V, TMR4_PWM_PDAR_IDX, (uint16_t)0x10);
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_2, TMR4_PWM_CH_V, TMR4_PWM_PDBR_IDX, (uint16_t)0x10);

    /* Start TMR4_2 count. */
    TMR4_Start(CM_TMR4_2);


/*=================================================================================*/
    LL_PERIPH_WP((LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU |LL_PERIPH_EFM | LL_PERIPH_SRAM));

    /* Enable TMR4_3 peripheral clock */
    FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4_3, ENABLE);

    /************************* Configure TMR4_3 counter *************************/
    stcTmr4Init.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK;//TMR4_CLK_SRC_EXTCLK  TMR4_CLK_SRC_INTERNCLK
    stcTmr4Init.u16ClockDiv = TMR4_CLK_DIV1;
    stcTmr4Init.u16CountMode = TMR4_MD_SAWTOOTH;
    stcTmr4Init.u16PeriodValue = PreValue;
    (void)TMR4_Init(CM_TMR4_3, &stcTmr4Init);

    /* Set TMR4_3 counter period buffer function */
    TMR4_PeriodBufCmd(CM_TMR4_3, ENABLE);

    /* Enable TMR4_3 peak interrupt */
    TMR4_IntCmd(CM_TMR4_3, TMR4_INT_CNT_PEAK, ENABLE);

    /************************* Configure TMR4_3_UH output-compare ******************/
    /* Initialize TMR4_3_UH OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_3_UH OC channel initialize */
    stcTmr4OcInit.u16CompareValue = PreValue>>1;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_3, TMR4_OC_CH_UH, &stcTmr4OcInit);

    /* TMR4_3_UH OC channel: compare mode OCMR */
    unTmr4OcOcmrh.OCMRx = (uint16_t)0x0;
    TMR4_OC_SetHighChCompareMode(CM_TMR4_3, TMR4_OC_CH_UH, unTmr4OcOcmrh);

    /* TMR4_3_UH OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_3, TMR4_OC_CH_UH, ENABLE);

    /************************* Configure TMR4_3_VH output-compare ******************/
    /* Initialize TMR4_3_VH OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_3_VH OC channel initialize */
    stcTmr4OcInit.u16CompareValue = PreValue>>1;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_3, TMR4_OC_CH_VH, &stcTmr4OcInit);

    /* TMR4_3_VH OC channel: compare mode OCMR */
    unTmr4OcOcmrh.OCMRx = (uint16_t)0x0;
    TMR4_OC_SetHighChCompareMode(CM_TMR4_3, TMR4_OC_CH_VH, unTmr4OcOcmrh);

    /* TMR4_3_VH OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_3, TMR4_OC_CH_VH, ENABLE);

    /************************* Configure TMR4_3_VL output-compare ******************/
    /* Initialize TMR4_3_VL OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_3_VL OC channel initialize */
    stcTmr4OcInit.u16CompareValue = PreValue>>1;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_3, TMR4_OC_CH_VL, &stcTmr4OcInit);

    /* TMR4_3_VL OC channel: compare mode OCMR */
    unTmr4OcOcmrl.OCMRx = (uint32_t)0x0;
    TMR4_OC_SetLowChCompareMode(CM_TMR4_3, TMR4_OC_CH_VL, unTmr4OcOcmrl);

    /* TMR4_3_VL OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_3, TMR4_OC_CH_VL, ENABLE);




    /************************* Configure TMR4_3_WH output-compare ******************/
    /* Initialize TMR4_3_WH OC structure */
    (void)TMR4_OC_StructInit(&stcTmr4OcInit);

    /* TMR4_3_WL OC channel initialize */
    stcTmr4OcInit.u16CompareValue = PreValue>>1;
    stcTmr4OcInit.u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
    stcTmr4OcInit.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
    stcTmr4OcInit.u16BufLinkTransObject = 0;
    (void)TMR4_OC_Init(CM_TMR4_3, TMR4_OC_CH_WL, &stcTmr4OcInit);
    (void)TMR4_OC_Init(CM_TMR4_3, TMR4_OC_CH_VL, &stcTmr4OcInit);

    /* TMR4_3_WL OC channel: compare mode OCMR */


    unTmr4OcOcmrl.OCMRx = (uint32_t)0x0;
    TMR4_OC_SetLowChCompareMode(CM_TMR4_3, TMR4_OC_CH_WL, unTmr4OcOcmrl);
    TMR4_OC_SetLowChCompareMode(CM_TMR4_3, TMR4_OC_CH_VL, unTmr4OcOcmrl);


    unTmr4OcOcmrl.OCMRx_f.OCFDCL  = TMR4_OC_OCF_SET; /* bit[0]     1  */
    unTmr4OcOcmrl.OCMRx_f.OCFPKL  = TMR4_OC_OCF_SET; /* bit[1]     1  */
    unTmr4OcOcmrl.OCMRx_f.OCFUCL  = TMR4_OC_OCF_SET; /* bit[2]     1  */
    unTmr4OcOcmrl.OCMRx_f.OCFZRL  = TMR4_OC_OCF_SET; /* bit[3]     1  */
    unTmr4OcOcmrl.OCMRx_f.OPDCL   = TMR4_OC_INVT;    /* bit[5:4]   11 */
    unTmr4OcOcmrl.OCMRx_f.OPPKL   = TMR4_OC_INVT;    /* bit[7:6]   11 */
    unTmr4OcOcmrl.OCMRx_f.OPUCL   = TMR4_OC_INVT;    /* bit[9:8]   11 */
    unTmr4OcOcmrl.OCMRx_f.OPZRL   = TMR4_OC_INVT;    /* bit[11:10] 11 */
    unTmr4OcOcmrl.OCMRx_f.OPNPKL  = TMR4_OC_HOLD;    /* bit[13:12] 00 */
    unTmr4OcOcmrl.OCMRx_f.OPNZRL  = TMR4_OC_HOLD;    /* bit[15:14] 00 */
    unTmr4OcOcmrl.OCMRx_f.EOPNDCL = TMR4_OC_HOLD;    /* bit[17:16] 00 */
    unTmr4OcOcmrl.OCMRx_f.EOPNUCL = TMR4_OC_HOLD;    /* bit[19:18] 00 */
    unTmr4OcOcmrl.OCMRx_f.EOPDCL  = TMR4_OC_INVT;    /* bit[21:20] 11 */
    unTmr4OcOcmrl.OCMRx_f.EOPPKL  = TMR4_OC_INVT;    /* bit[23:22] 11 */
    unTmr4OcOcmrl.OCMRx_f.EOPUCL  = TMR4_OC_INVT;    /* bit[25:24] 11 */
    unTmr4OcOcmrl.OCMRx_f.EOPZRL  = TMR4_OC_INVT;    /* bit[27:26] 11 */
    unTmr4OcOcmrl.OCMRx_f.EOPNPKL = TMR4_OC_HOLD;    /* bit[29:28] 00 */
    unTmr4OcOcmrl.OCMRx_f.EOPNZRL = TMR4_OC_HOLD;    /* bit[31:30] 00 */
    TMR4_OC_SetLowChCompareMode(CM_TMR4_3, TMR4_OC_CH_WL, unTmr4OcOcmrl);   
    TMR4_OC_SetLowChCompareMode(CM_TMR4_3, TMR4_OC_CH_VL, unTmr4OcOcmrl);   


    /* TMR4_3_WL OC channel: enable output-compare */
    TMR4_OC_Cmd(CM_TMR4_3, TMR4_OC_CH_WL, ENABLE);
    TMR4_OC_Cmd(CM_TMR4_3, TMR4_OC_CH_VL, ENABLE);

    /************************* Configure TMR4_3_V PWM *****************************/
    /* TMR4_3_V PWM: initialize */
    (void)TMR4_PWM_StructInit(&stcTmr4PwmInit);
    stcTmr4PwmInit.u16Mode = TMR4_PWM_MD_DEAD_TMR;
    stcTmr4PwmInit.u16ClockDiv = TMR4_PWM_CLK_DIV1;
    stcTmr4PwmInit.u16Polarity = TMR4_PWM_OXH_INVT_OXL_HOLD;//TMR4_PWM_OXH_HOLD_OXL_HOLD
    (void)TMR4_PWM_Init(CM_TMR4_3, TMR4_PWM_CH_V, &stcTmr4PwmInit);

    /* TMR4_3_V PWM: set dead time count */
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_3, TMR4_PWM_CH_V, TMR4_PWM_PDAR_IDX, (uint16_t)0x0);
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_3, TMR4_PWM_CH_V, TMR4_PWM_PDBR_IDX, (uint16_t)0x0);

    /************************* Configure TMR4_3_W PWM *****************************/
    /* TMR4_3_W PWM: initialize */
    (void)TMR4_PWM_StructInit(&stcTmr4PwmInit);
    stcTmr4PwmInit.u16Mode = TMR4_PWM_MD_DEAD_TMR;
    stcTmr4PwmInit.u16ClockDiv = TMR4_PWM_CLK_DIV1;
//    stcTmr4PwmInit.u16Polarity = TMR4_PWM_OXH_INVT_OXL_INVT;//TMR4_PWM_OXH_HOLD_OXL_HOLD
    (void)TMR4_PWM_Init(CM_TMR4_3, TMR4_PWM_CH_W, &stcTmr4PwmInit);
     (void)TMR4_PWM_Init(CM_TMR4_3, TMR4_PWM_CH_V, &stcTmr4PwmInit);

    /* TMR4_3_W PWM: set dead time count */
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_3, TMR4_PWM_CH_W, TMR4_PWM_PDAR_IDX, (uint16_t)0x10);
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_3, TMR4_PWM_CH_W, TMR4_PWM_PDBR_IDX, (uint16_t)0x10);

    TMR4_PWM_SetDeadTimeValue(CM_TMR4_3, TMR4_PWM_CH_V, TMR4_PWM_PDAR_IDX, (uint16_t)0x10);
    TMR4_PWM_SetDeadTimeValue(CM_TMR4_3, TMR4_PWM_CH_V, TMR4_PWM_PDBR_IDX, (uint16_t)0x10);

    /************************* Configure TMR4_3_VH event ***************************/
    /* TMR4_3_VH event: initialize */

    (void)TMR4_EVT_StructInit(&stcTmr4EventInit);
    stcTmr4EventInit.u16MatchCond = TMR4_EVT_MATCH_CNT_UP;//TMR4_EVT_MATCH_CNT_PEAK   TMR4_EVT_MATCH_CNT_UP
    stcTmr4EventInit.u16OutputEvent = TMR4_EVT_OUTPUT_EVT0;
    stcTmr4EventInit.u16CompareValue = PreValue>>1;
    (void)TMR4_EVT_Init(CM_TMR4_3, TMR4_EVT_CH_UH, &stcTmr4EventInit);

    /* Start TMR4_3 count. */
    TMR4_Start(CM_TMR4_3);


    /* Specifies the hard trigger for the specified ADC sequence. */
    ADC_TriggerConfig(CM_ADC1, ADC_SEQ_B, ADC_HARDTRIG_EVT0);

    /* Specifies the trigger event. */
    AOS_SetTriggerEventSrc(AOS_ADC1_0, EVT_SRC_TMR4_3_SCMP_UH);//ADC_EVT_SRC //EVT_SRC_TMR4_3_SCMP_VH

    /* Enable the sequence A trigger function of ADC. */
    ADC_TriggerCmd(CM_ADC1, ADC_SEQ_B, ENABLE);


////////////////ADC部分
   (void)GPIO_StructInit(&stcGpioInit);
    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
    (void)GPIO_Init(ADC_PORT, ADC_PIN|GPIO_PIN_02|GPIO_PIN_03, &stcGpioInit);
    (void)GPIO_Init(ADC_PORT, ADC_PIN1, &stcGpioInit);
    /* Enable ADC peripheral clock */
    ADC_FCG_ENABLE();

    /* Initializes ADC. */
    (void)ADC_StructInit(&stcAdcInit);

    stcAdcInit.u16ScanMode = ADC_MD_SEQA_CONT_SEQB_SINGLESHOT;
    (void)ADC_Init(ADC_UNIT, &stcAdcInit);

    /* Enable AOS peripheral clock */
    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_AOS, ENABLE);

    /* Specifies the hard trigger for the specified ADC sequence. */
    ADC_TriggerConfig(ADC_UNIT, ADC_SEQ_B, ADC_HARDTRIG_EVT0);

    /* Specifies the trigger event. */
    AOS_SetTriggerEventSrc(ADC_TRIG_SEL, ADC_EVT_SRC);

    /* Enable the sequence A trigger function of ADC. */
    ADC_TriggerCmd(ADC_UNIT, ADC_SEQ_B, ENABLE);


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