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No, not at all. We still have to perform the next check which is Layout Vs Schematic Check (LVS). This LVS tool will extract the schematic netlist and compare with the layout netlist. This is sometimes referred to as layout parameter extraction. LVS就是用来对比你的schematic和你的layout是不是一致的。虽然大部分时候你都觉得我的连线肯定是正确的，但是……你是人嘛！人肯定有可能出错的。不过，几十年前，还没有LVS的时代，据说真的是靠人工检查的……不过那会电路的device远远少于现在啊！ Please do not CONFUSE this with Layout Parasitic Extraction. They are DIFFERENT.
3.5 Layout Vs Schematic - LVS 1. In the Schematicwindow, press p. The Add Pin window will appear as shown below. Under Pin Names, type Vin. Make sure that the direction is input. Take note: We have to add pins to our schematic before we can run LVS successfully.
2. Continue to add the other 3 pins: VDD, GND and Vout. Your schematic will resemble the one shown below. Kindly let me know if you encounter any difficulties. Take note: The direction for VDD and GND is inputoutput but Vout will be output.
WAIT! What must you DO after making valid changes to your schematic? Save your schematic by pressing............I think you should know already. I am very proud of you. Let's continue. 3. In the Layout window, go to Calibre, Setup and then Netlist Export. The window will appear as shown below. For the field under Include File, type: /net/wildar/software2/local/library/AMIS/AMIS05_CDS/MSD_PDK/lib/amis500cx/tech/calibre/amis500cxakxx/current/box.cdl
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