Place & route求助

只看该作者 · 2012-4-17 13:04

本帖最后由 zuphen 于 2012-4-17 13:06 编辑

我使用ISE13.1花费在Router上的时间超级长，不知道为什么。
下面是提示信息：
Starting Router

Phase  1  : 101373 unrouted;    REAL time: 48 secs
Phase  2  : 57601 unrouted;    REAL time: 57 secs
Phase  3  : 15565 unrouted;    REAL time: 1 mins 38 secs
Phase  4  : 15909 unrouted; (Setup:121642, Hold:10911824, Component Switching Limit:0)    REAL time: 1 mins 58 secs
Updating file: Top_sch.ncd with current fully routed design.
Phase  5  : 0 unrouted; (Setup:95201, Hold:9815817, Component Switching Limit:0)    REAL time: 2 mins 33 secs
Phase  6  : 0 unrouted; (Setup:91979, Hold:9815817, Component Switching Limit:0)    REAL time: 2 mins 41 secs
Updating file: Top_sch.ncd with current fully routed design.
Phase  7  : 0 unrouted; (Setup:39095, Hold:9775319, Component Switching Limit:0)    REAL time: 3 mins 59 secs
Phase  8  : 0 unrouted; (Setup:39095, Hold:9775319, Component Switching Limit:0)    REAL time: 3 mins 59 secs
WARNING:Route:466 - Unusually high hold time violation detected among 2156 connections. The top 20 such instances are printed below. The
router will continue and try to fix it
DSP_inst/BRAM_din<27>:BMUX -> BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:A1 -7389
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI6 -7389
DSP_inst/BRAM_din<18>:DQ -> BRAM_dina<18>:A4 -7348
BRAM_dina<18>:A ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI0 -7348
DSP_inst/BRAM_din<27>:CMUX -> BRAM_dina<25>:A1 -7275
BRAM_dina<25>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIPADIP1
-7275
BRAM_dina<25>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIPADIP0
-7275
BRAM_dina<25>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIPADIP1
-7247
BRAM_dina<25>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIPADIP0
-7247
DSP_inst/BRAM_din<27>:BQ -> BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:A4 -7213
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:A ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI5 -7213
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:A ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI5 -7179
BRAM_dina<18>:A ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI0 -7147
BRAM_dina<18>:A ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[85].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI0 -7140
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[84].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI6 -7121
DSP_inst/BRAM_din<18>:DMUX -> BRAM_dina<18>:A1 -7118
BRAM_dina<18>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI1 -7118
DSP_inst/BRAM_din<11>:BMUX -> BRAM_dina<1>:D1 -7116
BRAM_dina<1>:DMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI2 -7116
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ena_array<14>:AMUX ->
BRAM_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram:DIADI6 -7045
PINFEED(215189,-166344) PINFEED(215189,-166408) PINFEED(181621,-134344) PINFEED(181621,-134408) PINFEED(96905,-118096) PINFEED(96905,-118160) PINFEED(96905,-53072) PINFEED(96905,-53136) PINFEED(215189,-150344) PINFEED(215189,-150408) PINFEED(181621,-118096) PINFEED(181621,-118160) PINFEED(96905,-37072) PINFEED(96905,-37136) PINFEED(181621,250240) PINFEED(181621,250240) PINFEED(181621,23944) PINFEED(181621,23944)
Phase  9  : 0 unrouted; (Setup:39163, Hold:107561, Component Switching Limit:0)    REAL time: 1 hrs 22 mins 27 secs
Phase 10  : 0 unrouted; (Setup:39165, Hold:107561, Component Switching Limit:0)    REAL time: 1 hrs 22 mins 29 secs
Total REAL time to Router completion: 1 hrs 22 mins 30 secs
Total CPU time to Router completion: 1 hrs 22 mins 36 secs

每次进行改动都要等N久，抗不住了，请问这种现象正常吗？小弟的机器配置也不是很低啊，4G的内存,XP32位，酷睿2_2.5G_4核（不过运行时只有一个核在工作，能启用其他核吗？）

只看该作者 · 2012-4-17 14:38

帮楼主顶一个，
望高手来作答

只看该作者 · 2012-4-19 08:56

1，你的工程大吗？用了多少资源？
2，时钟多少M，在什么片子上，做了一些约束了没？
3，是不是在布局布线的设置中选中了额外的努力等这类选项。(可以尝试用默认设置)

只看该作者 · 2012-4-19 14:39

3# Backkom80

先感谢LS大神的帮忙：
1、资源使用情况：

Slice Logic Utilization	Utilization
Number of Slice Registers	3%
Number used as Flip Flops
Number used as Latches
Number used as Latch-thrus
Number used as AND/OR logics
Number of Slice LUTs	7%
Number used as logic	5%
Number using O6 output only
Number using O5 output only
Number using O5 and O6
Number used as ROM
Number used as Memory	2%
Number used as Dual Port RAM
Number using O6 output only
Number using O5 output only
Number using O5 and O6
Number used as Single Port RAM
Number used as Shift Register
Number using O6 output only
Number using O5 output only
Number using O5 and O6
Number used exclusively as route-thrus
Number with same-slice register load
Number with same-slice carry load
Number with other load
Number of occupied Slices	12%
Number of LUT Flip Flop pairs used
Number with an unused Flip Flop	30%
Number with an unused LUT	24%
Number of fully used LUT-FF pairs	44%
Number of unique control sets
Number of slice register sites lost to control set restrictions	1%
Number of bonded IOBs	16%
Number of LOCed IOBs	100%
IOB Master Pads
IOB Slave Pads
Number of RAMB36E1/FIFO36E1s	33%
Number using RAMB36E1 only
Number using FIFO36E1 only
Number of RAMB18E1/FIFO18E1s	0%
Number of BUFG/BUFGCTRLs	12%
Number used as BUFGs
Number used as BUFGCTRLs
Number of ILOGICE1/ISERDESE1s	9%
Number used as ILOGICE1s
Number used as ISERDESE1s
Number of OLOGICE1/OSERDESE1s	13%
Number used as OLOGICE1s
Number used as OSERDESE1s
Number of BSCANs	25%
Number of BUFHCEs	0%
Number of BUFIODQSs	11%
Number of BUFRs	5%
Number of LOCed BUFRs	100%
Number of CAPTUREs	0%
Number of DSP48E1s	1%
Number of EFUSE_USRs	0%
Number of FRAME_ECCs	0%
Number of GTXE1s	0%
Number of IBUFDS_GTXE1s	0%
Number of ICAPs	0%
Number of IDELAYCTRLs	16%
Number of IODELAYE1s	12%
Number of LOCed IODELAYE1s	11%
Number of MMCM_ADVs	8%
Number of PCIE_2_0s	0%
Number of STARTUPs	100%
Number of SYSMONs	0%
Number of TEMAC_SINGLEs	0%

只看该作者 · 2012-4-19 14:45

2、时钟有2个microblaze用的100MHz，外围部分用的是61.44MHz；100MHz的没有做时钟周期约束，61.44MHz的做了时钟周期约束。
3、布局布线effort level ：high和standard都选过，standard会快一些，但还是会超过1小时

只看该作者 · 2012-4-19 14:48

3# Backkom80

关于时钟周期约束我有一些疑问：
我的时钟是这样一个过程，如附件，我的时钟周期约束应当加在什么地方？目前是加在clk_ab_p上的，我总感觉应当加在clk_ab_61_44MHz这里

只看该作者 · 2012-4-19 14:51

唉，头痛，还不得不看。:$

只看该作者 · 2012-4-19 14:53

1，加在clk_ab_p和sysclk_100上，后面的衍生时钟会自动约束，只要约束源时钟就可以了。
2，似乎IO利用率好高啊，100%？我没有看错吧，尝试将一些不要的IO去了试试呢。

只看该作者 · 2012-4-19 15:06

还有一个，在布局布线的设置中，这项是不是勾了：map slice logic into unused block rams，如果这个选了，布局布线时间也会加长很多，

只看该作者 · 2012-4-19 17:29

9# Backkom80

map slice logic into unused block rams没有勾上。

IO使用率100%我自己也有点奇怪，我本身设计中没有使用这么多的IO，不知道为什么会是100%。

另外，“加在clk_ab_p和sysclk_100上，后面的衍生时钟会自动约束，只要约束源时钟就可以了。”这个我不是很理解，因为源时钟和衍生时钟之间有delay模块，也有锁相环，所以clk_ab_p和clk_ab_61_44MHz之间应当会存在相位差的吧，这样自动约束也没有问题吗？