`timescale 10ns/1ns
module fpga_ccd(clk,sh,s1,s2,rs,clr,cp);//模块名fpga_ccd，s1即1E，s2即2E
input clk,clr;//输入端口为clk、clr,clr是为方便编程及复位而设置
output sh,s1,s2,rs,cp;//输出端口
reg[11:0] count;//设置count为12位reg型用于对时钟个数技数
reg[4:0] bb;//bb,ars都是中间临时变量
reg[4:0] ars;
reg sh,s1,s2,cp,rs;//设置输出变量数据类型
[email=always@(posedge]always@(posedge[/email] clk or negedge clr)//使ars保持1~8的反复循环
begin
if(clr==0)
ars=1;
else
if(count==0)
ars=1;
else
if(ars==8)
ars=1;
else
ars=ars+1;
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(count>8&&count<32)//使cp在9~31个时钟周期内为低电位
cp=0;
else
cp=(ars<3&&count>0)?1:0;//使得cp保持占空比为1：3的循环
end
[email=always@(negedge]always@(negedge[/email] clk)
begin
if(count>8&&count<32)//使rs在9~31个时钟周期内为低电位
rs=0;
else
rs=(ars<3&&ars>0)?1:0;//使rs保持占空比为1：3的循环
end
[email=always@(posedge]always@(posedge[/email] clk or negedge clr)//使count保持0~3824的循环
begin
if(clr==0)
count<=0;
else
if(count==3824)
count<=0;
else
count<=count+1;
end
[email=always@(posedge]always@(posedge[/email] clk)//使sh在第13~27时钟周期内为高电平其余时为低
begin
if(count>12&&count<28)
sh<=1;
else
sh<=0;
end
[email=always@(posedge]always@(posedge[/email] clk)//使s1、s2在0~40时钟周期内分别是高低电平且在之后是按照占空比为50%的脉冲进行
begin
if(clr==0)
bb=0;
s1=(count<40)?(1):bb[4];
s2=~s1;
else
bb=(count<41)?0:bb+1;
s1=(count<40)?(1):bb[4];
s2=~s1;
end
endmodule
这是最近看的一个已经发表过的硕士论文中的程序，为什么我直接编译这个程序总是不能通过呢？百思不得其解，望哪位大牛给解答一下？
错误显示首先在else那一行：Error (10170): Verilog HDL syntax error at fpga_ccd.v(65) near text "else"; expecting "@", or "end", or an identifier ("else" is a reserved keyword ), or a system task, or "{", or a sequential statement,
然后是上面模块的那一行，错误显示：Error (10112): Ignored module "fpga_ccd" at fpga_ccd.v(2) due to previous errors。 |
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