HotCRC CRC16R_8408_FFFF_0000 FPGA模块 HotPower@163.com（菜农独创）

/*-----------------------------------------------------------------------------------------------

      HotCRC CRC16R_8408_FFFF_0000 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 12:02:01

-----------------------------------------------------------------------------------------------*/

module CRC16R_8408(clk, rst, data, outcrc16)

input clk, rst;

input [7:0] data;

output reg[15:0] outcrc16;

reg [15:0] crc16;



task CRC16R_8408;

inout[15:0] crc16;

input[7:0] indata;

    crc16 = crc16[15:8] ^ CRC16R_8408_Table(crc16[7:0] ^ indata);

endtask



function [15:0] CRC16R_8408_Table;

    input [7:0] data;

    CRC16R_8408_Table = CRC16R_8408_Table0(data[1:0]) ^ CRC16R_8408_Table1(data[3:2]) ^ CRC16R_8408_Table2(data[5:4]) ^ CRC16R_8408_Table3(data[7:6]);

endfunction



function [15:0] CRC16R_8408_Table0;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_8408_Table0 = 16'h0000; 2'b01: CRC16R_8408_Table0 = 16'h1189; 2'b10: CRC16R_8408_Table0 = 16'h2312; 2'b11: CRC16R_8408_Table0 = 16'h329B;

        default: CRC16R_8408_Table0 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16R_8408_Table1;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_8408_Table1 = 16'h0000; 2'b01: CRC16R_8408_Table1 = 16'h4624; 2'b10: CRC16R_8408_Table1 = 16'h8C48; 2'b11: CRC16R_8408_Table1 = 16'hCA6C;

        default: CRC16R_8408_Table1 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16R_8408_Table2;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_8408_Table2 = 16'h0000; 2'b01: CRC16R_8408_Table2 = 16'h1081; 2'b10: CRC16R_8408_Table2 = 16'h2102; 2'b11: CRC16R_8408_Table2 = 16'h3183;

        default: CRC16R_8408_Table2 = 16'h0000;

    endcase

endfunction



function [15:0] CRC16R_8408_Table3;

    input[1:0] data;

    case(data)

        2'b00: CRC16R_8408_Table3 = 16'h0000; 2'b01: CRC16R_8408_Table3 = 16'h4204; 2'b10: CRC16R_8408_Table3 = 16'h8408; 2'b11: CRC16R_8408_Table3 = 16'hC60C;

        default: CRC16R_8408_Table3 = 16'h0000;

    endcase

endfunction





always [url=home.php?mod=space&uid=72445]@[/url] (posedge clk or negedge rst)

begin

    if (!rst)

    begin

        crc16 <= 16'hFFFF;

    end

    else

    begin

        CRC16R_8408(crc16, data);

        outcrc16 <= crc16;

        crc16 <= crc16;

    end

end

endmodule