/*-----------------------------------------------------------------------------------------------
HotCRC CRC64R_D800000000000000_0000000000000000_0000000000000000 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 12:10:15
-----------------------------------------------------------------------------------------------*/
module CRC64R_D800000000000000(clk, rst, data, outcrc64)
input clk, rst;
input [7:0] data;
output reg[63:0] outcrc64;
reg [63:0] crc64;
task CRC64R_D800000000000000;
inout[63:0] crc64;
input[7:0] indata;
crc64 = crc64[63:8] ^ CRC64R_D800000000000000_Table(crc64[7:0] ^ indata);
endtask
function [63:0] CRC64R_D800000000000000_Table;
input [7:0] data;
CRC64R_D800000000000000_Table = CRC64R_D800000000000000_Table0(data[1:0]) ^ CRC64R_D800000000000000_Table1(data[3:2]) ^ CRC64R_D800000000000000_Table2(data[5:4]) ^ CRC64R_D800000000000000_Table3(data[7:6]);
endfunction
function [63:0] CRC64R_D800000000000000_Table0;
input[1:0] data;
case(data)
2'b00: CRC64R_D800000000000000_Table0 = 64'h0000000000000000; 2'b01: CRC64R_D800000000000000_Table0 = 64'h01B0000000000000; 2'b10: CRC64R_D800000000000000_Table0 = 64'h0360000000000000; 2'b11: CRC64R_D800000000000000_Table0 = 64'h02D0000000000000;
default: CRC64R_D800000000000000_Table0 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;
endcase
endfunction
function [63:0] CRC64R_D800000000000000_Table1;
input[1:0] data;
case(data)
2'b00: CRC64R_D800000000000000_Table1 = 64'h0000000000000000; 2'b01: CRC64R_D800000000000000_Table1 = 64'h06C0000000000000; 2'b10: CRC64R_D800000000000000_Table1 = 64'h0D80000000000000; 2'b11: CRC64R_D800000000000000_Table1 = 64'h0B40000000000000;
default: CRC64R_D800000000000000_Table1 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;
endcase
endfunction
function [63:0] CRC64R_D800000000000000_Table2;
input[1:0] data;
case(data)
2'b00: CRC64R_D800000000000000_Table2 = 64'h0000000000000000; 2'b01: CRC64R_D800000000000000_Table2 = 64'h1B00000000000000; 2'b10: CRC64R_D800000000000000_Table2 = 64'h3600000000000000; 2'b11: CRC64R_D800000000000000_Table2 = 64'h2D00000000000000;
default: CRC64R_D800000000000000_Table2 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;
endcase
endfunction
function [63:0] CRC64R_D800000000000000_Table3;
input[1:0] data;
case(data)
2'b00: CRC64R_D800000000000000_Table3 = 64'h0000000000000000; 2'b01: CRC64R_D800000000000000_Table3 = 64'h6C00000000000000; 2'b10: CRC64R_D800000000000000_Table3 = 64'hD800000000000000; 2'b11: CRC64R_D800000000000000_Table3 = 64'hB400000000000000;
default: CRC64R_D800000000000000_Table3 = 64'h0000_0000_0000_0000_0000_0000_0000_0000;
endcase
endfunction
always [url=home.php?mod=space&uid=72445]@[/url] (posedge clk or negedge rst)
begin
if (!rst)
begin
crc64 <= 64'h0000000000000000;
end
else
begin
CRC64R_D800000000000000(crc64, data);
outcrc64 <= crc64;
crc64 <= crc64;
end
end
endmodule
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