本帖最后由 34af9uc 于 2024-3-29 18:55 编辑
<div class="blockcode"><blockquote>/*************************与非门*************************/
/**************************************************/
/**************************************************/
`timescale 1ns/10ps
module nand_gate_4bits(A, B, Y);
input[3:0] A;
input[3:0] B;
output[3:0] Y;
assign Y=~(A&B);
endmodule
/*******************testbench of nand_gate******************/
module nand_gate_4bits_tb;
reg[3:0] aa, bb;
wire[3:0] yy;
//nand_gate nand_gate(.A(aa), .B(bb), .Y(yy));
nand_gate_4bits nand_gate_4bits(.A(aa), .B(bb), .Y(yy));
initial
begin
aa<=4'b0000;bb<=4'b0000;
#10 aa<=4'b1111;bb<=4'b0000;
#10 aa<=4'b0000;bb<=4'b11_00;
#10 aa<=4'b0011;bb<=4'b0000;
#10 aa<=4'b1100;bb<=4'b0011;
$stop;
end
endmodule
/**************************************************/
/**************************************************/
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