求教

[复制链接]
1851|1
手机看帖
扫描二维码
随时随地手机跟帖
caoqing1314|  楼主 | 2012-5-20 15:32 | 显示全部楼层 |阅读模式
module caoxing(L,A,B);
    input A,B;
    output L;
    supply1 Vdd;
    supply0 GND;
    wire W1;
    pmos(L,Vdd,A);
    pmos(L,Vdd,B);
    nmos(L,W1,B);
    nmos(W1,GND,A);
endmodule

为什么含有CMOS等的编译就报错:
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 7): cannot synthesize MOS switch gate primitive
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 8): cannot synthesize MOS switch gate primitive
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 9): cannot synthesize MOS switch gate primitive
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 10): cannot synthesize MOS switch gate primitive

相关帖子

GoldSunMonkey| | 2012-5-20 23:53 | 显示全部楼层
他不支持MOS电路的综合

使用特权

评论回复
发新帖 我要提问
您需要登录后才可以回帖 登录 | 注册

本版积分规则

0

主题

100

帖子

1

粉丝