module caoxing(L,A,B);
input A,B;
output L;
supply1 Vdd;
supply0 GND;
wire W1;
pmos(L,Vdd,A);
pmos(L,Vdd,B);
nmos(L,W1,B);
nmos(W1,GND,A);
endmodule
为什么含有CMOS等的编译就报错:
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 7): cannot synthesize MOS switch gate primitive
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 8): cannot synthesize MOS switch gate primitive
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 9): cannot synthesize MOS switch gate primitive
Error (10014): Verilog HDL unsupported feature error at file "caoxing.v" (line 10): cannot synthesize MOS switch gate primitive |
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