我用modesim仿真
register.v:
module register8(ena,clk,data,rst,out);
input ena,clk,rst;
input [7:0] data;
output [7:0] out;
wire [7:0] data;
reg[7:0] out;
always @(posedge clk)
if (!rst)
out <= 0;
else if (ena)
out <= data;
//閾忕晫鍔у▽鈩冩箒閸愭獔lse妞ょ櫢绱濋弰鍓у姧婵″倹鐏塭na娑撹桨缍嗛悽闈涢挬閿涘苯宓嗘担鎸庢闁界喎褰夐崠鏍电礉data閸欐ê瀵查敍灞肩稻out娴犲秳绻氶幐浣风瑝閸?
endmodule
`timescale 1 ns/ 100 ps
module register8_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk;
reg [7:0] data;
reg ena;
reg rst;
// wires
wire [7:0] out;
// assign statements (if any)
register8 i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.data(data),
.ena(ena),
.out(out),
.rst(rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
clk=0;
#5 clk=~clk;
// --> end
end
initial
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
#10 rst=0;
#10 rst=1;
#10 ena=1;
#10 data <= 16'h55;
#10 data<=16'haa;
#10 data<=16'h46;
#10 $stop;
// --> end
end
endmodule
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