仲裁阶段的波特率 CAN FD Freq / (Sync_Seg + Pro_Seg + Phase_Seg1 + Phase_Seg2)数据阶段的波特率 CAN FD Freq / (Sync_Seg + Pro_Seg + Phase_Seg1 + Phase_Seg2)
这样计算有什么问题吗？为何这样配置M467的公式不对呢？
CLK_SetModuleClock(CANFD0_MODULE, CLK_CLKSEL0_CANFD0SEL_HCLK, CLK_CLKDIV5_CANFD0(10));
20MHz时钟，那么单位Tq就是50ns。
下面的计算是：1M/10M?
psCanfd->NBTP = (3 << 25) + // NSJW = 3+1 =4 CLK
(10 << 16) + // NBRP = 0+10 =10 // prescaler = 10
(13 << 8) + // NTSG1 = 13+1 =14 CLK
(5 - 1) ; // NTSG2 = 5 CLK // One bit = 1+14+5 = 20 CLK
// Date rate is configured as following. If CAN frame, following code is void
psCanfd->DBTP = ((4 - 1) << 16) + // DBRP = 4 prescaler
((17 - 1) << 8) + // DTSG1 = 17 CLK
((3 - 1) << 4) + // DTSG2 = 3 CLK // One bit = 17+3 = 20 CLK
(3 - 1) ; // DSJW = 3 CLK |
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