我用lattice diamond 启动modelsim时提示Error loading design：
# Reading pref.tcl
# do {D:/mcu/yongrenxin/FPGA/LATTICE/20240710V1.0/ch310/smbus_simplify_tb/smbus_simplify_tb.mdo}
# Loading project smbus_simplify_tb
# Model Technology ModelSim - Lattice FPGA Edition vlog 2023.3 Compiler 2023.07 Jul 18 2023
# Start time: 14:16:19 on Jul 22,2024
# vlog -reportprogress 300 "+incdir+D:/mcu/yongrenxin/FPGA/LATTICE/20240710V1.0/ch310" -work work D:/mcu/yongrenxin/FPGA/LATTICE/20240710V1.0/ch310/SMBUS_Simplify.v
# -- Compiling module smbus_2
#
# Top level modules:
# smbus_2
# End time: 14:16:19 on Jul 22,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Lattice FPGA Edition vlog 2023.3 Compiler 2023.07 Jul 18 2023
# Start time: 14:16:19 on Jul 22,2024
# vlog -reportprogress 300 "+incdir+D:/mcu/yongrenxin/FPGA/LATTICE/20240710V1.0/ch310" -work work D:/mcu/yongrenxin/FPGA/LATTICE/20240710V1.0/ch310/smbus_simplify_tb.v
# -- Compiling module smbus_simplify_tb
#
# Top level modules:
# smbus_simplify_tb
# End time: 14:16:19 on Jul 22,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -L work -L pmi_work -L ovi_machxo smbus_simplify_tb
# Start time: 14:16:20 on Jul 22,2024
# ** License Issue: License request for latticemsim feature failed
# ** License Issue: Invalid license file syntax. (C:\MentorGraphics\LICENSE.TXT)
# ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: 'latticemsim' or 'alteramtivlog'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO D:\mcu\yongrenxin\FPGA\LATTICE\20240710V1.0\ch310\smbus_simplify_tb\smbus_simplify_tb.mdo PAUSED at line 14
不知哪位大神能否帮忙看看，是何原因？
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