本人最近做了一个小波变换的FPGA实现 用的是ISE10.1 用的板子是xilinx V2的板子。最后综合报告出来之后 对timing report有些疑问。通常来说，
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 6.286ns (frequency: 159.076MHz)
Total number of paths / destination ports: 268605 / 3770
-------------------------------------------------------------------------
Delay: 3.143ns (Levels of Logic = 5)
clock period 和Delay是相等的，为什么我的是两倍的关系呢？？？
timing report如下所示：
Timing Summary:
---------------
Speed Grade: -7
Minimum period: 6.286ns (Maximum Frequency: 159.076MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 5.521ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 6.286ns (frequency: 159.076MHz)
Total number of paths / destination ports: 268605 / 3770
-------------------------------------------------------------------------
Delay: 3.143ns (Levels of Logic = 5)
Source: im_show_inst/vga_inst/Hcount_6 (FF)
Destination: rrom/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_1 (FF)
Source Clock: clk rising 0.3X
Destination Clock: clk rising 0.7X
Data Path: im_show_inst/vga_inst/Hcount_6 to rrom/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 6 0.370 0.581 im_show_inst/vga_inst/Hcount_6 (im_show_inst/vga_inst/Hcount_6)
LUT4_L:I0->LO 1 0.275 0.118 im_show_inst/vga_inst/Start_Video56 (im_show_inst/vga_inst/Start_Video56)
LUT4:I2->O 2 0.275 0.416 im_show_inst/vga_inst/Start_Video57 (im_show_inst/vga_inst/Start_Video57)
LUT4_D:I3->O 1 0.275 0.349 im_show_inst/vga_inst/Start_Video83_1 (im_show_inst/vga_inst/Start_Video83)
LUT4:I2->O 5 0.275 0.000 mux2_1_inst/d_out<15>1 (src_addr<15>)
begin scope: 'rrom'
begin scope: 'BU2'
FDE:D 0.208 U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_1
----------------------------------------
Total 3.143ns (1.678ns logic, 1.465ns route)
(53.4% logic, 46.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 123 / 27
-------------------------------------------------------------------------
Offset: 5.521ns (Levels of Logic = 5)
Source: rrom/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (FF)
Destination: B<7> (PAD)
Source Clock: clk rising 0.7X
Data Path: rrom/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 to B<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 16 0.370 0.766 U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>)
LUT3:I0->O 1 0.275 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_3 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_3)
MUXF5:I1->O 6 0.303 0.543 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_2_f5 (douta(0))
end scope: 'BU2'
end scope: 'rrom'
LUT3:I1->O 3 0.275 0.397 im_show_inst/RGB_inst/B<0>1 (B_0_OBUF)
OBUF:I->O 2.592 B_0_OBUF (B<0>)
----------------------------------------
Total 5.521ns (3.815ns logic, 1.706ns route)
(69.1% logic, 30.9% route)
========================================================================= |
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