STM32H745I通常通过外部存储控制器（FMC）与SDRAM进行连接。FMC提供了多个存储器接口，包括SDRAM接口，支持多种SDRAM类型，如SDR SDRAM、DDR SDRAM和LPDDR SDRAM。这使得STM32H745I能够灵活地与不同类型的SDRAM进行通信。
三、读写操作前的准备- 初始化设置：在使用STM32H745I进行SDRAM读写操作之前，需要对SDRAM进行初始化设置。这包括配置FMC控制器的时序参数、刷新周期和读写延迟等。具
的初始化过程可以参考STM32H7的官方文档和参考手册
驱动STM32H745I-DISCO开发板上安装的MT48LC4M32B2B5-6A SDRAM外部存储器。
SDRAM存储器接口。它包含使用BSP_SDRAM_Initialization_sequence()函数对外部SDRAM设备进行编程的SDRAM初始化序列。请注意，此序列对于所有SDRAM设备都是标准的，但不同设备之间可能存在一些差异。如果确实存在这种情况，应单独实现正确的序列。
SDRAM读写操作：
一旦初始化完成，就可以通过读写操作访问外部SDRAM存储器。
可以使用AHB访问通过BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData()函数执行读写操作，或者通过MDMA传输使用BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA()函数。
AHB访问以32位宽事务执行，MDMA传输配置固定为单字（无突发）传输（请参阅SDRAM_MspInit()静态函数）。
用户可以实现自己的读写访问函数，以使用所需的配置。
如果使用中断模式进行MDMA传输，则在MDMA传输完成时，将在IRQ处理程序文件中调用BSP_SDRAM_MDMA_IRQHandler()函数来处理生成的中断。
您可以使用BSP_SDRAM_Sendcmd()函数在运行时向SDRAM设备发送命令，并给出作为参数的所需命令，该命令在“FMC_SDRAM_CommandTypeDef”结构中预定义。
SDARAM的初始化代码
地址映射：确保SDRAM的地址映射正确，以便STM32H745I能够准确地访问存储单元。[url=]复制[/url]
#include "stm32h745i_discovery_sdram.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32H745I_DISCO
* @{
*/
/** @defgroup STM32H745I_DISCO_SDRAM SDRAM
* @{
*/
/** @defgroup STM32H745I_DISCO_SDRAM_Exported_Variables Exported Variables
* @{
*/
SDRAM_HandleTypeDef hsdram[SDRAM_INSTANCES_NBR];
/**
* @}
*/
/** @defgroup STM32H745I_DISCO_SDRAM_Private_Variables Private Variables
* @{
*/
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
static uint32_t IsMspCallbacksValid = 0;
#endif
/**
* @}
*/
/** @defgroup STM32H745I_DISCO_SDRAM_Private_Function_Prototypes Private Functions Prototypes
* @{
*/
static void SDRAM_MspInit(SDRAM_HandleTypeDef *hSdram);
static void SDRAM_MspDeInit(SDRAM_HandleTypeDef *hSdram);
/**
* @}
*/
/** @defgroup STM32H745I_DISCO_SDRAM_Exported_Functions Exported Functions
* @{
*/
/**
* @brief Initializes the SDRAM device.
* @param Instance SDRAM Instance
* @retval BSP status
*/
int32_t BSP_SDRAM_Init(uint32_t Instance)
{
int32_t ret = BSP_ERROR_NONE;
static MT48LC4M32B2_Context_t pRegMode;
if(Instance >=SDRAM_INSTANCES_NBR)
{
ret = BSP_ERROR_WRONG_PARAM;
}
else
{
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
/* Register the SDRAM MSP Callbacks */
if(IsMspCallbacksValid == 0)
{
if(BSP_SDRAM_RegisterDefaultMspCallbacks(Instance) != BSP_ERROR_NONE)
{
return BSP_ERROR_PERIPH_FAILURE;
}
}
#else
/* Msp SDRAM initialization */
SDRAM_MspInit(&hsdram[Instance]);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
if(MX_SDRAM_BANK2_Init(&hsdram[Instance],FMC_SDRAM_ROW_BITS_NUM_12, FMC_SDRAM_MEM_BUS_WIDTH_16) != HAL_OK)
{
ret = BSP_ERROR_NO_INIT;
}
else
{
/* External memory mode register configuration */
pRegMode.TargetBank = FMC_SDRAM_CMD_TARGET_BANK2;
pRegMode.RefreshMode = MT48LC4M32B2_AUTOREFRESH_MODE_CMD;
pRegMode.RefreshRate = REFRESH_COUNT;
pRegMode.BurstLength = MT48LC4M32B2_BURST_LENGTH_1;
pRegMode.BurstType = MT48LC4M32B2_BURST_TYPE_SEQUENTIAL;
pRegMode.CASLatency = MT48LC4M32B2_CAS_LATENCY_3;
pRegMode.OperationMode = MT48LC4M32B2_OPERATING_MODE_STANDARD;
pRegMode.WriteBurstMode = MT48LC4M32B2_WRITEBURST_MODE_SINGLE;
/* SDRAM initialization sequence */
if(MT48LC4M32B2_Init(&hsdram[Instance], &pRegMode) != MT48LC4M32B2_OK)
{
ret = BSP_ERROR_COMPONENT_FAILURE;
}
}
}
return ret;
}
/**
* @brief DeInitializes the SDRAM device.
* @param Instance SDRAM Instance
* @retval BSP status
*/
int32_t BSP_SDRAM_DeInit(uint32_t Instance)
{
int32_t ret = BSP_ERROR_NONE;
if(Instance >= SDRAM_INSTANCES_NBR)
{
ret = BSP_ERROR_WRONG_PARAM;
}
else
{
(void)HAL_SDRAM_DeInit(&hsdram[Instance]);
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 0)
/* SDRAM controller de-initialization */
SDRAM_MspDeInit(&hsdram[Instance]);
#endif /* (USE_HAL_SDRAM_REGISTER_CALLBACKS == 0) */
}
return ret;
}
/**
* @brief Initializes the SDRAM periperal.
* @param hSdram SDRAM handle
* @param RowBitsNumber Number of row to set
* @param MemoryDataWidth The momory width 16 or 32bits
* @retval HAL status
*/
__weak HAL_StatusTypeDef MX_SDRAM_BANK2_Init(SDRAM_HandleTypeDef *hSdram, uint32_t RowBitsNumber, uint32_t MemoryDataWidth)
{
FMC_SDRAM_TimingTypeDef sdram_timing;
/* SDRAM device configuration */
hsdram->Instance = FMC_SDRAM_DEVICE;
/* SDRAM handle configuration */
hSdram->Init.SDBank = FMC_SDRAM_BANK2;
hSdram->Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
hSdram->Init.RowBitsNumber = RowBitsNumber;
hSdram->Init.MemoryDataWidth = MemoryDataWidth;
hsdram->Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hSdram->Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
hSdram->Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hSdram->Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hSdram->Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
hSdram->Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
/* Timing configuration for as SDRAM */
sdram_timing.LoadToActiveDelay = 2;
sdram_timing.ExitSelfRefreshDelay = 7;
sdram_timing.SelfRefreshTime = 4;
sdram_timing.RowCycleDelay = 7;
sdram_timing.WriteRecoveryTime = 2;
sdram_timing.RPDelay = 2;
sdram_timing.RCDDelay = 2;
/* SDRAM controller initialization */
if(HAL_SDRAM_Init(hSdram, &sdram_timing) != HAL_OK)
{
return HAL_ERROR;
}
return HAL_OK;
}
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Default BSP SDRAM Msp Callbacks
* @param Instance SDRAM Instance
* @retval BSP status
*/
int32_t BSP_SDRAM_RegisterDefaultMspCallbacks (uint32_t Instance)
{
int32_t ret = BSP_ERROR_NONE;
/* Check if the instance is supported */
if(Instance >= SDRAM_INSTANCES_NBR)
{
ret = BSP_ERROR_WRONG_PARAM;
}
else
{
/* Register MspInit/MspDeInit Callbacks */
if(HAL_SDRAM_RegisterCallback(&hsdram[Instance], HAL_SDRAM_MSP_INIT_CB_ID, SDRAM_MspInit) != HAL_OK)
{
ret = BSP_ERROR_PERIPH_FAILURE;
}
if(HAL_SDRAM_RegisterCallback(&hsdram[Instance], HAL_SDRAM_MSP_DEINIT_CB_ID, SDRAM_MspDeInit) != HAL_OK)
{
ret = BSP_ERROR_PERIPH_FAILURE;
}
else
{
IsMspCallbacksValid = 1;
}
}
/* Return BSP status */
return ret;
}
/**
* @brief BSP SDRAM Msp Callback registering
* @param Instance SDRAM Instance
* @param CallBacks pointer to MspInit/MspDeInit callbacks functions
* @retval BSP status
*/
int32_t BSP_SDRAM_RegisterMspCallbacks (uint32_t Instance, BSP_SDRAM_Cb_t *CallBacks)
{
int32_t ret = BSP_ERROR_NONE;
/* Check if the instance is supported */
if(Instance >= SDRAM_INSTANCES_NBR)
{
ret = BSP_ERROR_WRONG_PARAM;
}
else
{
/* Register MspInit/MspDeInit Callbacks */
if(HAL_SDRAM_RegisterCallback(&hsdram[Instance], HAL_SDRAM_MSP_INIT_CB_ID, CallBacks->pMspInitCb) != HAL_OK)
{
ret = BSP_ERROR_PERIPH_FAILURE;
}
if(HAL_SDRAM_RegisterCallback(&hsdram[Instance], HAL_SDRAM_MSP_DEINIT_CB_ID, CallBacks->pMspDeInitCb) != HAL_OK)
{
ret = BSP_ERROR_PERIPH_FAILURE;
}
else
{
IsMspCallbacksValid = 1;
}
}
/* Return BSP status */
return ret;
}
#endif /* (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) */
/**
* @brief Sends command to the SDRAM bank.
* @param Instance SDRAM Instance
* @param SdramCmd Pointer to SDRAM command structure
* @retval BSP status
*/
int32_t BSP_SDRAM_SendCmd(uint32_t Instance, FMC_SDRAM_CommandTypeDef *SdramCmd)
{
int32_t ret;
if(Instance >= SDRAM_INSTANCES_NBR)
{
ret = BSP_ERROR_WRONG_PARAM;
}
else if(MT48LC4M32B2_Sendcmd(&hsdram[Instance], SdramCmd) != MT48LC4M32B2_OK)
{
ret = BSP_ERROR_PERIPH_FAILURE;
}
else
{
ret = BSP_ERROR_NONE;
}
return ret;
}
/**
* @brief This function handles SDRAM MDMA interrupt request.
* @param Instance SDRAM instance
* @retval None
*/
void BSP_SDRAM_IRQHandler(uint32_t Instance)
{
HAL_MDMA_IRQHandler(hsdram[Instance].hmdma);
}
/**
* @}
*/
/** @defgroup STM32H745I_DISCO_SDRAM_Private_Functions Private Functions
* @{
*/
/**
* @brief Initializes SDRAM MSP.
* @param hSdram SDRAM handle
* @retval None
*/
static void SDRAM_MspInit(SDRAM_HandleTypeDef *hSdram)
{
static MDMA_HandleTypeDef mdma_handle;
GPIO_InitTypeDef gpio_init_structure;
/* Enable FMC clock */
__HAL_RCC_FMC_CLK_ENABLE();
/* Enable chosen MDMAx clock */
SDRAM_MDMAx_CLK_ENABLE();
/* Enable GPIOs clock */
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
/* Common GPIO configuration */
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
gpio_init_structure.Pull = GPIO_PULLUP;
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
gpio_init_structure.Alternate = GPIO_AF12_FMC;
/* GPIOD configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
/* GPIOF configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
/* GPIOH configuration */
gpio_init_structure.Pin = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 ;
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
// /* Configure common MDMA parameters */
// mdma_handle.Init.Request = MDMA_REQUEST_SW;
// mdma_handle.Init.TransferTriggerMode = MDMA_BLOCK_TRANSFER;
// mdma_handle.Init.Priority = MDMA_PRIORITY_HIGH;
// mdma_handle.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
// mdma_handle.Init.SourceInc = MDMA_SRC_INC_WORD;
// mdma_handle.Init.DestinationInc = MDMA_DEST_INC_WORD;
// mdma_handle.Init.SourceDataSize = MDMA_SRC_DATASIZE_WORD;
// mdma_handle.Init.DestDataSize = MDMA_DEST_DATASIZE_WORD;
// mdma_handle.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
// mdma_handle.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
// mdma_handle.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
// mdma_handle.Init.BufferTransferLength = 128;
// mdma_handle.Init.SourceBlockAddressOffset = 0;
// mdma_handle.Init.DestBlockAddressOffset = 0;
// mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;
// /* Associate the DMA handle */
// __HAL_LINKDMA(hsdram, hmdma, mdma_handle);
// /* Deinitialize the stream for new transfer */
// HAL_MDMA_DeInit(&mdma_handle);
// /* Configure the DMA stream */
// HAL_MDMA_Init(&mdma_handle);
// /* NVIC configuration for DMA transfer complete interrupt */
// HAL_NVIC_SetPriority(SDRAM_MDMAx_IRQn, 0x0F, 0);
// HAL_NVIC_EnableIRQ(SDRAM_MDMAx_IRQn);
}
/**
* @brief DeInitializes SDRAM MSP.
* @param hSdram SDRAM handle
* @retval None
*/
static void SDRAM_MspDeInit(SDRAM_HandleTypeDef *hSdram)
{
static MDMA_HandleTypeDef mdma_handle;
/* Prevent unused argument(s) compilation warning */
UNUSED(hSdram);
/* Disable NVIC configuration for DMA interrupt */
HAL_NVIC_DisableIRQ(SDRAM_MDMAx_IRQn);
/* Deinitialize the stream for new transfer */
mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;
(void)HAL_MDMA_DeInit(&mdma_handle);
}
四、读写操作- 读操作：从SDRAM中读取数据的过程。在发送读命令后，需要等待一定的时间（如CAS潜伏期）才能获取到数据。
- 写操作：向SDRAM中写入数据的过程。写操作也需要在正确的时序下进行，以确保数据能够正确地写入存储单元。需要注意的是，写操作并不是即时的，因为选通三极管与电容的充电需要一定的时间。
测试代码
[url=]复制[/url]
if(BSP_SDRAM_Init(0) != BSP_ERROR_NONE)
{
printf("SDRAM Initialization : FAILED.\r\n");
printf("SDRAM Test Aborted.\r\n");
}
else
{
printf("SDRAM Initialization : OK.\r\n");
}
/* Fill the buffer to write */
Fill_Buffer(sdram_aTxBuffer, BUFFER_SIZE, 0xA244250F);
/* Write data to the SDRAM memory */
if(HAL_SDRAM_Write_32b(&hsdram[0], (uint32_t *)(SDRAM_WRITE_READ_ADDR + WRITE_READ_ADDR), (uint32_t*)sdram_aTxBuffer, BUFFER_SIZE) != BSP_ERROR_NONE)
{
printf("SDRAM WRITE : FAILED.\r\n");
printf("SDRAM Test Aborted.\r\n");
}
else
{
printf("SDRAM WRITE : OK.\r\n");
}
/* Read back data from the SDRAM memory */
if(HAL_SDRAM_Read_32b(&hsdram[0], (uint32_t *)(SDRAM_WRITE_READ_ADDR + WRITE_READ_ADDR), (uint32_t*)sdram_aRxBuffer, BUFFER_SIZE) != BSP_ERROR_NONE)
{
printf("SDRAM READ : FAILED.\r\n");
printf("SDRAM Test Aborted.\r\n");
}
else
{
printf("SDRAM READ : OK.\r\n");
}
if(Buffercmp(sdram_aTxBuffer, sdram_aRxBuffer, BUFFER_SIZE) > 0)
{
printf("SDRAM COMPARE : FAILED.\r\n");
printf("SDRAM Test Aborted.\r\n");
}
else
{
printf("SDRAM Test : OK.\r\n");
}
|
楼主
标题置顶
标题高亮
