always @(posedge sys_clk0 ) begin
s1 <= clk_init; //CLK_pwm
s2 <= s1; //0
end
assign pose_sclk=!s2&s1; //
always @(posedge sys_clk0 or negedge rst_n)
if(~rst_n) begin
rst_n<=1'b1;
clk_100m<=1'b0;
state_d<=WAIT;
end
else begin if(pose_sclk) // 上升沿
state_d<=A;
else case(state_d) //0
A:begin
clk_100m<=1'b1;
state_d<=B;
end
B:begin
clk_100m<=1'b0;
state_d<=WAIT;
end
WAIT:begin
clk_100m<=1'b0;
end
default: state_d <= WAIT;
endcase
end
always @(posedge sys_clk0 ) begin
s1 <= clk_init; //CLK_pwm
s2 <= s1; //0
end
assign pose_sclk=!s2&s1; //
always @(posedge sys_clk0 or negedge rst_n)
if(~rst_n) begin
rst_n<=1'b1;
clk_100m<=1'b0;
state_d<=WAIT;
end
else begin if(pose_sclk) // 上升沿
state_d<=A;
else case(state_d) //0
A:begin
clk_100m<=1'b1;
state_d<=B;
end
B:begin
clk_100m<=1'b0;
state_d<=WAIT;
end
WAIT:begin
clk_100m<=1'b0;
end
default: state_d <= WAIT;
endcase
end
always @(posedge sys_clk0 ) begin
s1 <= clk_init; //CLK_pwm
s2 <= s1; //0
end
assign pose_sclk=!s2&s1; //
always @(posedge sys_clk0 or negedge rst_n)
if(~rst_n) begin
rst_n<=1'b1;
clk_100m<=1'b0;
state_d<=WAIT;
end
else begin if(pose_sclk) // 上升沿
state_d<=A;
else case(state_d) //0
A:begin
clk_100m<=1'b1;
state_d<=B;
end
B:begin
clk_100m<=1'b0;
state_d<=WAIT;
end
WAIT:begin
clk_100m<=1'b0;
end
default: state_d <= F;
endcase
end
50Mhz晶振，sys_clk0 倍频100Mhz，clk_init作为输入脉冲信号1Khz-100Khz。在clk_init上升沿输出clk_100m高低变化一次。发现clk_100m有抖动。
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楼主
