我用CAP1做捕捉外部AD7658的BUSY信号，有的时候上电可以正常捕捉，有的时候上电就不能捕捉，请问这是什么原因引起的呀，我都调试了快一个月了，其他中断都没有就是专门AD采样！
我的EV.C配置：
void InitEv(void)
{
/**************************************/
/*** Configure the EXTCONA registers ***/
/**************************************/
EvaRegs.EXTCONA.all = 0x0000;
/*
bit 15-4 0's: reserved
bit 3 0: EVSOCE, 0 = disable EV start of ADC conversion output
bit 2 0: QEPIE, 0 = disable CAP3_QEPI as index input
bit 1 0: QEPIQUAL, 0 = CAP3_QEPI qual disabled
bit 0 1: INDCOE, 1 = independent compare enable
*/
EvbRegs.EXTCONB.all = 0x0000;
/*
bit 15-4 0's: reserved
bit 3 0: EVSOCE, 0 = disable EV start of ADC conversion output
bit 2 0: QEPIE, 0 = disable CAP6_QEPI as index input
bit 1 0: QEPIQUAL, 0 = CAP6_QEPI qual disabled
bit 0 1: INDCOE, 1 = independent compare enable
*/
/******************************************************/
/*** Disable and clear all event manager interrupts ***/
/******************************************************/
EvaRegs.EVAIMRA.all = 0x0000; // Disable all EVA group A interrupts
EvaRegs.EVAIMRB.all = 0x0000; // Disable all EVA group B interrupts
EvaRegs.EVAIMRC.all = 0x0000; // Disable all EVA group C interrupts
EvaRegs.EVAIFRA.all = 0xFFFF; // Clear all EVA group A interrupts
EvaRegs.EVAIFRB.all = 0xFFFF; // Clear all EVA group B interrupts
EvaRegs.EVAIFRC.all = 0xFFFF; // Clear all EVA group C interrupts
EvbRegs.EVBIMRA.all = 0x0000; // Disable all EVB group A interrupts
EvbRegs.EVBIMRB.all = 0x0000; // Disable all EVB group B interrupts
EvbRegs.EVBIMRC.all = 0x0000; // Disable all EVB group C interrupts
EvbRegs.EVBIFRA.all = 0xFFFF; // Clear all EVB group A interrupts
EvbRegs.EVBIFRB.all = 0xFFFF; // Clear all EVB group B interrupts
EvbRegs.EVBIFRC.all = 0xFFFF; // Clear all EVB group C interrupts
// EvaRegs.COMCONA.all = 0xCA00;
/**
bit 15 1: Compare enable
bit 14-13 10: Compare register reload condition
bit 12 0: Space vector PWM Mode enable
bit 11-10 10: Action control register reload
bit 9 1: Compare output enable
bit 8 0: Current status of the PDPINTA pin
bit 7:0 00000000: reserved
**/
/**************************************/
/*** Configure the GPTCONA register ***/
/**************************************/
EvaRegs.GPTCONA.all = 0x0000;
/*
bit 15 0: reserved
bit 14 0: T2STAT, read-only
bit 13 0: T1STAT, read-only
bit 12 0: T2CTRIPE, 0=disable timer2 compare trip
bit 11 0: T1CTRIPE, 0=disable timer1 compare trip
bit 10-9 00: T2TOADC, no events trigger ADC
bit 8-7 00: T1TOADC, period interrupt flag trigger ADC
bit 6 0: TCOMPOE, no effective because of EvaRegs.EXTCONA(0)=1
bit 5 0: T2COMPOE, 0 = timer2 compare HI-z'd
bit 4 0: T1COMPOE, 1 = timer1 compare output enable
bit 3-2 00: T2PIN, 00 = forced low
bit 1-0 00: T1PIN, 10 = active high
*/
/************************************************************/
/*** Configure Timer 1 for timebase of capture1 ***/
/************************************************************/
EvaRegs.T1CON.all = 0x0000;
EvaRegs.T1CNT = 0x0000;
EvaRegs.T1PR = Period;
EvaRegs.T1CON.all = 0x0848; // Init T1CON, enable timer
/*
bit 15-14 00: FREE/SOFT, 00 = stop immediately on emulator suspend
bit 13 0: reserved
bit 12-11 01: TMODEx, 10 = continous-up count mode
bit 10-8 000: TPSx, 111 = x/128 prescaler,011 = x/8 prescaler
bit 7 0: T2SWT1, 0 = use own TENABLE bit
bit 6 1: TENABLE, 1 = enable timer
bit 5-4 00: TCLKS, 00 = HSPCLK is clock source
bit 3-2 10: TCLD, 00 = reload compare reg immediately
bit 1 0: TECMPR, 1 = enable timer compare
bit 0 0: SELT1PR, 0 = use own period register
*/
/************************************************************/
/*** Configure Timer 2 as the trigger counter of phase AB ***/
/************************************************************/
EvaRegs.T2CON.all = 0x0000;
EvaRegs.T2CNT = 0x0000;
EvaRegs.T2PR = Period;
EvaRegs.T2CON.all = 0x1748; // Init T2CON, enable timer
/*
bit 15-14 00: FREE/SOFT, 00 = stop immediately on emulator suspend
bit 13 0: reserved
bit 12-11 10: TMODEx, 10 = continous-up count mode
bit 10-8 111: TPSx, 111 = x/128 prescaler
bit 7 0: T2SWT1, 0 = use own TENABLE bit
bit 6 1: TENABLE, 1 = enable timer
bit 5-4 00: TCLKS, 00 = HSPCLK is clock source
bit 3-2 10: TCLD, 10 = reload compare reg immediately
bit 1 0: TECMPR, 1 = enable timer compare
bit 0 0: SELT1PR, 0 = use own period register
*/
/**************************************/
/*** Configure the GPTCONB register ***/
/**************************************/
EvbRegs.GPTCONB.all = 0x0000;
/*
bit 15 0: reserved
bit 14 0: T4STAT, read-only
bit 13 0: T3STAT, read-only
bit 12 0: T4CTRIPE, 0=disable timer2 compare trip
bit 11 0: T3CTRIPE, 0=disable timer1 compare trip
bit 10-9 00: T4TOADC
bit 8-7 00: T3TOADC
bit 6 0: TCOMPOE, 0 = Hi-z all timer compare outputs;
bit 5 0: T4COMPOE, 0 = timer2 compare HI-z'd
bit 4 1: T3COMPOE, 0 = timer1 compare HI-z'd
bit 3-2 00: T4PIN, 00 = forced low;
bit 1-0 00: T3PIN, 10 = active high;
*/
/************************************************************/
/*** Configure Timer 3 for timebase of capture6 and as the trigger counter of phase B***/
/************************************************************/
EvbRegs.T3CON.all = 0x0000;
EvbRegs.T3CNT = 0x0000;
EvbRegs.T3PR = Period;
EvbRegs.T3CON.all = 0x1748; // Init T3CON, enable timer
/*
bit 15-14 00: FREE/SOFT, 00 = stop immediately on emulator suspend
bit 13 0: reserved
bit 12-11 10: TMODEx, 10 = continous-up count mode
bit 10-8 111: TPSx, 111 = x/128 prescaler
bit 7 0: T2SWT1, 0 = use own TENABLE bit
bit 6 1: TENABLE, 1 = enable timer
bit 5-4 00: TCLKS, 00 = HSPCLK is clock source
bit 3-2 10: TCLD, 10 = reload compare reg immediately
bit 1 0: TECMPR, 1 = enable timer compare
bit 0 0: SELT1PR, 0 = use own period register
*/
/************************************************************/
/*** Configure Timer 4 as the trigger counter of phase C***/
/************************************************************/
EvbRegs.T4CON.all = 0x0000;
EvbRegs.T4CNT = 0x0000;
EvbRegs.T4PR = Period;
EvbRegs.T4CON.all = 0x1748; // Init T3CON, enable timer
/*
bit 15-14 00: FREE/SOFT, 00 = stop immediately on emulator suspend
bit 13 0: reserved
bit 12-11 10: TMODEx, 10 = continous-up count mode
bit 10-8 111: TPSx, 111 = x/128 prescaler
bit 7 0: T2SWT1, 0 = use own TENABLE bit
bit 6 0: TENABLE, 1 = enable timer
bit 5-4 00: TCLKS, 00 = HSPCLK is clock source
bit 3-2 10: TCLD, 00 = reload compare reg immediately
bit 1 0: TECMPR, 1 = enable timer compare
bit 0 0: SELT1PR, 0 = use own period register
*/
/************************************************************/
/*** Configure capture 1、3 ***/
/************************************************************/
EvaRegs.CAPCONA.all = 0x0000; //Reset Capture
EvaRegs.CAPFIFOA.all =0x0000;
EvaRegs.CAPFIFOA.bit.CAP1FIFO =01;
/*
bit 15-14 00: reserved
bit 13-12 01: have one value in CAP1FIFO
bit 11-10 00: empty
bit 9-8 00: empty
bit 7-0 00000000: reserved
*/
// EvaRegs.CAPFIFOA.bit.CAP3FIFO =01;
/*
bit 15-14 00: reserved
bit 13-12 01: have one value in CAP3FIFO
bit 11-10 00: empty
bit 9-8 00: empty
bit 7-0 00000000: reserved
*/
EvaRegs.CAPCONA.all = 0xA440;//xs0xA440;//1010 0100 0100 0000
/*
bit 15 1: no operation
bit 14-13 01: enable CAP1/2
bit 12 0: enable CAP3
bit 11 0: reserved
bit 10 1: select timer 1 as capture3 timebase
bit 9 0: select timer 2 as capture12 timebase
bit 8 0: start ADC converton when flag is set
bit 7-6 01: capture1 detects rising edges
bit 5-4 00: no detect
bit 3-2 00: capture3 detects falling edges
bit 1-0 00: reserved
*/
/************************************************************/
/*** Configure capture 4、6 to trigger the SEQ2 ***/
/************************************************************/
EvbRegs.CAPCONB.all = 0x0000;
EvbRegs.CAPFIFOB.all =0x0000;
// EvbRegs.CAPFIFOB.bit.CAP4FIFO =01;
/*
bit 15-14 00: reserved
bit 13-12 01: have one value in CAP4FIFO
bit 11-10 00: empty
bit 9-8 00: empty
bit 7-0 00000000: reserved
*/
EvbRegs.CAPFIFOB.bit.CAP6FIFO =01;
/*
bit 15-14 00: reserved
bit 13-12 01: have one value in CAP6FIFO
bit 11-10 00: empty
bit 9-8 00: empty
bit 7-0 00000000: reserved
*/
EvbRegs.CAPCONB.all =0x9408;
/*
bit 15 1: no operation
bit 14-13 00: enable CAP4/5
bit 12 1: enable CAP6
bit 11 0: reserved
bit 10 1: select timer 3 as capture6 timebase
bit 9 0: select timer 4 as capture4 timebase
bit 8 0: start ADC converton when flag is set
bit 7-6 00: detects falling edges
bit 5-4 00: no detect
bit 3-2 10: detects falling edges
bit 1-0 00: reserved
*/
/***enable capture1 interrupt***/
EvaRegs.EVAIMRC.bit.CAP1INT =1;
PieCtrlRegs.PIEIER3.bit.INTx5 = 1;
IER |= 0x0004;
} // end InitEv() |
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