- spi3_peripheral_config();
- /* spi3 io output enable */
- spi_quad_io23_output_enable(SPI3);
- /* spi3 quad enable */
- spi_quad_enable(SPI3);
- /* spi3 quad write enable */
- spi_quad_write_enable(SPI3);
- /* spi3 quad write access byte enable */
- spi_byte_access_enable(SPI3);
- /* spi3 quad write access word disable */
- spi_word_access_disable(SPI3);
- /* FIFO level set 4-data frame */
- spi_fifo_threshold_level_set(SPI3, SPI_FIFO_TH_04DATA);
- /* configure SPI data frame size */
- spi_i2s_data_frame_size_config(SPI3, SPI_DATASIZE_8BIT);
- /* configure SPI data frame size */
- spi_current_data_num_config(SPI3, 0);
- /* spi3 enable */
- spi_enable(SPI3);
-
- /* set nss low */
- SET_SPI3_NSS_LOW
- //spi_dma_enable(SPI3, SPI_DMA_RECEIVE);
- //spi_dma_enable(SPI3, SPI_DMA_TRANSMIT);
- /* Polling SPI TP flag */
- while(spi_i2s_flag_get(SPI3, SPI_FLAG_TP) == RESET){};
- /* Polling SPI TC flag */
- while(spi_i2s_flag_get(SPI3, SPI_FLAG_TC) == RESET){};
- spi_i2s_data_transmit(SPI3, 0xEE);
- /* SPI master start transfer */
- spi_master_transfer_start(SPI3, SPI_TRANS_START);
- /* wait DMA transmit complete */
- //while(dma_flag_get(DMA0, DMA_CH4, DMA_FLAG_FTF) == RESET){};
-
- /*Polling SPI TC flag */
- while(spi_i2s_flag_get(SPI3, SPI_FLAG_TC) == RESET){};
- /* Clear DMA Transfer Complete Flags */
- //dma_flag_clear(DMA0, DMA_CH4, DMA_FLAG_FTF);
- /* set nss high */
- SET_SPI3_NSS_HIGH
|
