always@(posedge clk)
begin
if(!reset)
begin
s=17'b0;
out=16'b0;
end
else
begin
s={data[7:0],9'b0};
begin
for(i=7;i>0;i=i-1)
begin
if(s[16]==0) //若第一位为0，左移一位；
s=s<<1;
else begin
s=s^17'b11000000000000101;/*若第一位为1，则与生成多项式进行异或操作；*/
s=s<<1; //左移一位；
end
end
out=s[15:0]; //s的后16位即为校验位；
end
end
end
endmodule
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: (0 5 12 16)
// * data width: 8
//
// Info : tools@easics.be
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module CRC16_D8;
// polynomial: (0 5 12 16)
// data width: 8
// convention: the first serial bit is D[7]
function [15:0] nextCRC16_D8;
input [7:0] Data;
input [15:0] crc;
reg [7:0] d;
reg [15:0] c;
reg [15:0] newcrc;
begin
d = Data;
c = crc;
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