[应用相关] AT32F402/405 DMA使用指南

int main(void)

{

  /* 初始化系统时钟 */

/* initial system clock */  

  system_clock_config();  

/* 板载初始化 */

  /* at board initial */

  at32_board_init();

  /* 打开DMA1时钟 */

  crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);



  /* dma1 通道初始化 */

  dma_reset(DMA1_CHANNEL1);

  dma_init_struct.buffer_size = BUFFER_SIZE;

  dma_init_struct.direction = DMA_DIR_MEMORY_TO_MEMORY;

  dma_init_struct.memory_base_addr = (uint32_t)dst_buffer;

  dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_WORD;

  dma_init_struct.memory_inc_enable = TRUE;

  dma_init_struct.peripheral_base_addr = (uint32_t)src_const_buffer;

  dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_WORD;

  dma_init_struct.peripheral_inc_enable = TRUE;

  dma_init_struct.priority = DMA_PRIORITY_MEDIUM;

  dma_init_struct.loop_mode_enable = FALSE;

  dma_init(DMA1_CHANNEL1, &dma_init_struct);



  /* 打开传输完成中断 */

  dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);



  /* dma1 channel1 interrupt nvic init */

  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);

  nvic_irq_enable(DMA1_Channel1_IRQn, 1, 0);



  dma_channel_enable(DMA1_CHANNEL1, TRUE);



  /* wait the end of transmission */

  while(data_counter_end != 0)

  {

  }

  /* check if the transmitted and received data are equal */

  transfer_status = buffer_compare(src_const_buffer, dst_buffer, BUFFER_SIZE);



  /* 判断数据是否正确，正确则点亮LED灯 */

  if(transfer_status == SUCCESS)

  {

    /* turn led2/led3/led4 on */

    at32_led_on(LED2);

    at32_led_on(LED3);

    at32_led_on(LED4);

  }



  while(1)

  {

  } 

#define BUFFER_SIZE     16

uint16_t src_buffer[BUFFER_SIZE] = {0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008, 

                                  0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010};

Int main(void)

{

  /* 系统时钟初始化 */

  system_clock_config();  

  /* 板载初始化 */

  at32_board_init();

  /* 开启 dma2/gpioc/tmr2 时钟 */

  crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);

  crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);

  crm_periph_clock_enable(CRM_TMR2_PERIPH_CLOCK, TRUE);

  

  /* config gpiob pin for output mode */

  gpio_init_struct.gpio_pins = GPIO_PINS_ALL;

  gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;

  gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;

  gpio_init_struct.gpio_pull = GPIO_PULL_NONE;

  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;

  gpio_init(GPIOB, &gpio_init_struct);

  /* 初始化TMR2 */

  tmr_base_init(TMR2, 0xFF, 0);

  tmr_cnt_dir_set(TMR2, TMR_COUNT_UP);

  

  /* 开启 TMR2溢出DMA请求 */

  tmr_dma_request_enable(TMR2, TMR_OVERFLOW_DMA_REQUEST, TRUE);

  

  /* dma2 通道1初始化 */

  dma_reset(DMA2_CHANNEL1);

  dma_init_struct.buffer_size = BUFFER_SIZE;

  dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;

  dma_init_struct.memory_base_addr = (uint32_t)src_buffer;

  dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;

  dma_init_struct.memory_inc_enable = TRUE;

  dma_init_struct.peripheral_base_addr = (uint32_t)&GPIOB->odt;

  dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;

  dma_init_struct.peripheral_inc_enable = FALSE;

  dma_init_struct.priority = DMA_PRIORITY_MEDIUM;

  dma_init_struct.loop_mode_enable = FALSE;

  dma_init(DMA2_CHANNEL1, &dma_init_struct);

  /* 开启传输完成中断 */

  dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);

  

  /* dma2 channel1 interrupt nvic init */

  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);

  nvic_irq_enable(DMA2_Channel1_IRQn, 1, 0);

  

  /*开启TMR2的DMAMUX功能 */

  dmamux_enable(DMA2, TRUE);

  dmamux_init(DMA2MUX_CHANNEL1, DMAMUX_DMAREQ_ID_TMR2_OVERFLOW);

  

  /* enable dma channel */

  dma_channel_enable(DMA2_CHANNEL1, TRUE);

  

  /* enable tmr2 */

  tmr_counter_enable(TMR2, TRUE);

  

  while(1)

  {

  }

}

int main(void)

{

  /* initial system clock */

  system_clock_config();



  /* at board initial */

  at32_board_init();



  /* enable dma2/gpioa clock */

  crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);

  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);



  /* config pa1 for input mode */

  gpio_init_struct.gpio_pins = GPIO_PINS_0;

  gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;

  gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;

  gpio_init_struct.gpio_pull = GPIO_PULL_NONE;

  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;

  gpio_init(GPIOA, &gpio_init_struct);



  scfg_exint_line_config(SCFG_PORT_SOURCE_GPIOA, SCFG_PINS_SOURCE0);



  exint_default_para_init(&exint_init_struct);

  exint_init_struct.line_enable = TRUE;

  exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;

  exint_init_struct.line_select = EXINT_LINE_0;

  exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;

  exint_init(&exint_init_struct);



  /* exint line1 interrupt nvic init */

  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);

  nvic_irq_enable(EXINT0_IRQn, 1, 0);



  /* dma2 channel4 configuration */

  dma_reset(DMA2_CHANNEL4);

  dma_init_struct.buffer_size = BUFFER_SIZE;

  dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;

  dma_init_struct.memory_base_addr = (uint32_t)dst_buffer;

  dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;

  dma_init_struct.memory_inc_enable = TRUE;

  dma_init_struct.peripheral_base_addr = (uint32_t)src_buffer;

  dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;

  dma_init_struct.peripheral_inc_enable = TRUE;

  dma_init_struct.priority = DMA_PRIORITY_MEDIUM;

  dma_init_struct.loop_mode_enable = FALSE;

  dma_init(DMA2_CHANNEL4, &dma_init_struct);



  /* genertor1 configuration */

  dmamux_generator_default_para_init(&dmamux_gen_init_struct);

  dmamux_gen_init_struct.gen_polarity = DMAMUX_GEN_POLARITY_RISING;

  dmamux_gen_init_struct.gen_request_number = 4;

  dmamux_gen_init_struct.gen_signal_sel = DMAMUX_GEN_ID_EXINT0;

  dmamux_gen_init_struct.gen_enable = TRUE;

  dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);



  /* enable transfer full data interrupt */

  dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);



  /* dma2 channel4 interrupt nvic init */

  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);

  nvic_irq_enable(DMA2_Channel4_IRQn, 1, 0);



  /* dmamux function enable */

  dmamux_enable(DMA2, TRUE);

  dmamux_init(DMA2MUX_CHANNEL4, DMAMUX_DMAREQ_ID_REQ_G1);



  /* enable dma channe4 */

  dma_channel_enable(DMA2_CHANNEL4, TRUE);



  while(1)

  {

  }

} 

 int main(void)

{

  /* initial system clock */

  system_clock_config();



  /* at board initial */

  at32_board_init();



  /* enable dma2/gpioa clock */

  crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);

  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);

  crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);



  /* config pa1 for input mode */

  gpio_init_struct.gpio_pins = GPIO_PINS_0;

  gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;

  gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;

  gpio_init_struct.gpio_pull = GPIO_PULL_NONE;

  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;

  gpio_init(GPIOA, &gpio_init_struct);



  scfg_exint_line_config(SCFG_PORT_SOURCE_GPIOA, SCFG_PINS_SOURCE0);



  exint_default_para_init(&exint_init_struct);

  exint_init_struct.line_enable = TRUE;

  exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;

  exint_init_struct.line_select = EXINT_LINE_0;

  exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;

  exint_init(&exint_init_struct);



  /* exint line1 interrupt nvic init */

  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);

  nvic_irq_enable(EXINT0_IRQn, 1, 0);



  /* dma2 channel4 configuration */

  dma_reset(DMA2_CHANNEL4);

  dma_init_struct.buffer_size = BUFFER_SIZE;

  dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;

  dma_init_struct.memory_base_addr = (uint32_t)dst_buffer;

  dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;

  dma_init_struct.memory_inc_enable = TRUE;

  dma_init_struct.peripheral_base_addr = (uint32_t)src_buffer;

  dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;

  dma_init_struct.peripheral_inc_enable = TRUE;

  dma_init_struct.priority = DMA_PRIORITY_MEDIUM;

  dma_init_struct.loop_mode_enable = FALSE;

  dma_init(DMA2_CHANNEL4, &dma_init_struct);



  dmamux_sync_default_para_init(&dmamux_sync_init_struct);

  dmamux_sync_init_struct.sync_request_number = 4;

  dmamux_sync_init_struct.sync_signal_sel = DMAMUX_SYNC_ID_EXINT0;

  dmamux_sync_init_struct.sync_polarity = DMAMUX_SYNC_POLARITY_RISING;

  dmamux_sync_init_struct.sync_event_enable = FALSE;

  dmamux_sync_init_struct.sync_enable = TRUE;

  dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);



  /* enable transfer full data interrupt */

  dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);



  /* dma2 channel4 interrupt nvic init */

  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);

  nvic_irq_enable(DMA2_Channel4_IRQn, 1, 0);



  /* dmamux function enable */

  dmamux_enable(DMA2, TRUE);

  dmamux_init(DMA2MUX_CHANNEL4, DMAMUX_DMAREQ_ID_TMR1_OVERFLOW);



  /* enable dma channe4 */

  dma_channel_enable(DMA2_CHANNEL4, TRUE);



  /* tmr1 configuration */

  tmr_base_init(TMR1, 5000, 5000);

  tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);



  /* enable tmr1 overflow edam request */

  tmr_dma_request_enable(TMR1, TMR_OVERFLOW_DMA_REQUEST, TRUE);



  /* enable tmr1 */

  tmr_counter_enable(TMR1, TRUE);

  while(1)

  {

  }

}