ACTEL FPGA 混合仿真求助

只看该作者 · 2012-7-5 10:27

以前的可综合模块用VHDL写的，仿真测试文件是用Verilog写的
源码级仿真提示实例失败

# Loading presynth.testbench
# Loading presynth.MX25L6445E
# ACTEL version supports only a single HDL
# ** Fatal: (vsim-3039) I:/Work/FPGA/work/250/FPGA210_V1/stimulus/testbench.v(186): Instantiation of 'TOP_FLASH' failed.
# Time: 0 ps Iteration: 0 Instance: /testbench File: I:/Work/FPGA/work/250/FPGA210_V1/stimulus/testbench.v
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 24

怎么解决！求助！