找到一个资料
PSoC1 I2C: Usage description with sleep
Last Updated: 02/24/2010
For all PSoC1 devices (CY8C20xxx, CY8C21xxx, CY8C22xxx, CY8C24xxx, CY8C27xxx, CY8C29xxx) it is highly recommended to restart the I2C block following the below procedure after coming out from sleep. This is to avoid ongoing I2C traffic in the bus to disrupt PSoC I2C block state machines.
Procedure to restart I2C block,
Step1: Disable I2C block (by clearing the ‘Enable’ bit in the I2C_CFG register)
Step1: Put I2C SDA & I2C SCL pins to ‘HI-Z Analog’ drive mode
Step2: Enable I2C block (set the ‘Enable’ bit in the I2C_CFG register)
Step3: Give delay equal to 4 I2C sample clock periods
Step4: Restore I2C SDA & I2C SCL pin drive modes back to OD-LOW
这是我根据资料写的程序
void i2c_restart(void)
{
BYTE i,j;
I2C_CFG &=~0x01;//disable i2c;
PRT1DM0 &=~0x03;
PRT1DM1 |=0x03;
PRT1DM2 &=~0x03;
I2C_CFG |=0x01;
for(i=0;i<100;i++)
for(j=0;j<120;j++);
PRT1DM0 |=0x03;
PRT1DM1 |=0x03;
PRT1DM2 |=0x03;
}
可是还是不行，是因为延时不等于 4 I2C sample clock periods吗？如果是这个时间怎么算
来个人吧！！
|
楼主
