一个小程序 VHDL 始终错误?

只看该作者 · 2012-9-19 13:01

PROCESS(reset,sys_clk)
BEGIN
      IF reset = '0' THEN
         cnt_s <= '0';
      ELSE
         IF cnt = 12345  THEN
            cnt_s <= '1'; -- 1t
         ELSE
            cnt_s <= '0';
         END IF;
      END IF;
END PROCESS;
Error d.vhd(237): couldn't implement registers for assignments on this clock edge

只看该作者 · 2012-9-19 13:04

PROCESS(sys_clk,newdata)
  BEGIN
   IF rising_edge(newdata) THEN
      case do is
         when x"10" => new_s(0) <= '1';
         when x"11" => new_s(1) <= '1';
         when x"12" => new_s(2) <= '1';
         when x"13" => new_s(3) <= '1';
         when others => null;
      end case;
   ELSE
         new_s <= (others => '0');
   END IF;
END PROCESS;
因為  newdata =1 時間不卻定,所以必須抓上緣 1個sys_clk,但是又錯誤......