求助，请帮忙看一下为什么总是运行不了，谢谢

只看该作者 · 2012-9-27 15:54

请各位帮忙看一下这两个并串转换的小程序，为什么总是运行不了，谢谢
第一个：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all; --并串转换
ENTITY bingchuan IS
PORT (RESET :IN STD_LOGIC;
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
DOUT :OUT STD_LOGIC
);
END bingchuan ;
architecture bhv of bingchuan is
SIGNAL COUNT : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL DAOUT : STD_LOGIC ;
BEGIN
PROCESS (CLK,COUNT,RESET)
BEGIN
IF RESET='1' THEN COUNT <= "000";
ELSIF COUNT="111" THEN
COUNT<="000";
ELSE COUNT<=COUNT+1;
END IF;
END PROCESS;
PROCESS(CLK,COUNT,RESET)
BEGIN
IF RESET='1' THEN COUNT<="000";
ELSIF CLK'EVENT AND CLK='1' THEN
CASE COUNT IS
WHEN "000"=>
DAOUT <=DIN(7);
WHEN "001"=>
DAOUT <=DIN(6);
WHEN "010"=>
DAOUT <=DIN(5);
WHEN "011"=>
DAOUT <=DIN(4);
WHEN "100"=>
DAOUT <=DIN(3);
WHEN "101"=>
DAOUT <=DIN(2);
WHEN "110"=>
DAOUT <=DIN(1);
WHEN "111"=>
DAOUT <=DIN(0);
END CASE ;
end IF;
END PROCESS ;
DOUT <= DAOUT ;
END bhv ;
第二个：
library ieee;
use ieee.Std_Logic_1164.all;
entity bch is
port
(
rst,clk : in Std_Logic;
ser : in Std_Logic_Vector (7 downto 0 );
par : out Std_Logic
);
end bch;
architecture bhv of bch is
variable i : integer range 0 to 7;
signal count:std_logic;
begin
process(clk,rst)
begin
if rst='1' then i:='0';
elsif clk 'event and clk='1' then
if i='7' then i:='0';
else i:=i+'1';
end if;
end if;
end process;
process(clk ,i,rst)
begin
if rst='1' then i:='0';
elsif clk 'event and clk<='1' then
case count is
when '0' =>
count<=per(0);
when '1' =>
count<=per(1);
when '2' =>
count<=per(2);
when '3' =>
count<=per(3);
when '4' =>
count<=per(4);
when '5' =>
count<=per(5);
when '6' =>
count<=per(6);
when '7' =>
count<=per(7);
when others=>i<='0';
end case;
end if;
end process;
ser<=count;
end bhv;