always @(state,clk2hz)
begin
case(state)
state0:blink[2:0]<='b111;
state1:blink[2]<=clk2hz;
state2:blink[1]<=clk2hz;
state3:blink[0]<=clk2hz;
default:blink[2:0]<='bx;
endcase
end
/*Warning (10240): Verilog HDL Always Construct warning at clock.v(166):
inferring latch(es) for variable "blink", which holds its previous value in one
or more paths through the always construct*/
这个warning怎么解决啊！
哪位大侠帮看下啊
谢啦 |
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