在DDR1 规范JEDEC79引脚定义中看到如下一段话：
“CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied upon 1st power up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self--refresh entry and exit, VREF must be maintained to this input The standard pinout includes one CKE pin.” 个人对其中描述的意思有些迷惑，请高手指点。 |
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