// Example of chaning the timing of XINTF Zones. // Note acutal values should be based on the hardware // attached to the zone - timings presented here are // for example purposes.
// All Zones: // Timing for all zones based on XTIMCLK = SYSCLKOUT XintfRegs.XINTCNF2.bit.XTIMCLK = 0; // XTIMCLK 0:= SYSCLKOUT 1:= 1/2 SYSCLKOUT XintfRegs.XINTCNF2.bit.CLKOFF = 0; // 0: enable CLKOUT 1: Disable CLKOUT XintfRegs.XINTCNF2.bit.CLKMODE = 0; // XCLKOUT 0:= XTIMCLK 1:= 1/2 XTIMCLK XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// Zone 0: // Change write access lead active trail timing // When using ready, ACTIVE must be 1 or greater // Lead must always be 1 or greater // Use timings based on SYSCLKOUT = XTIMCLK XintfRegs.XTIMING0.bit.USEREADY = 0; XintfRegs.XTIMING0.bit.XWRTRAIL = 3; XintfRegs.XTIMING0.bit.XWRACTIVE = 7; XintfRegs.XTIMING0.bit.XWRLEAD = 2; XintfRegs.XTIMING0.bit.XRDTRAIL= 3; XintfRegs.XTIMING0.bit.XRDACTIVE = 7; XintfRegs.XTIMING0.bit.XRDLEAD = 2; // Do not double lead/active/trail for Zone 0 XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone 2 is slow, so add additional BCYC cycles when ever switching // from Zone 2 to another Zone. This will help avoid // bus contention. XintfRegs.XBANK.bit.BCYC = 2; XintfRegs.XBANK.bit.BANK = 2; // 2 }