[22]Y.A.Chapuis,J.P.Blonde,and F.Braun,“FPGA implementation by modular design reuse mode to optimize hardware architecture and performance of ac motor controller algorithm,”in Proc.EPE-PEMC Conf.,Sep.2004,pp.134–142,CD-ROM.
[23]T.Riesgo,Y.Torroja,and E.de la Torre,“Design methodologies based on hardware description languages,”IEEE.Trans.Ind.Electron.,vol.46, no.1,pp.3–12,Feb.1999.
[24]M.Cirstea,“Electronic systems integrated modelling and optimized digital controller prototyping—A novel(HDL)approach,”IEEE Ind.Electron. Soc.Newslett., vol.52, no.3,pp.11–13,Sep.2005.
[25]L.Charaabi,E.Monmasson,and I.Slama-Belkhodja,“Presentation of an efficient design methodology to develop IP-core functions for control systems:Application to the design of an antiwindup PI controller,” in Proc.IEEE IECON,Seville, Spain,Nov. 2002,pp.1942–1947,CD-ROM.
[26]J.C.G.Pimentel and H.Le-Huy,“A VHDL-based methodology to develop high performance servo drivers,”in Conf.Rec.IEEE IAS Annu.Meeting, Rome,Italy,Oct. 2000,pp.1505–1512.
[27]D.L.Perry,VHDL.New York:McGraw-Hill,2004.
[28]T.Grandpierre,C.Lavarenne,and Y.Sorel,“Optimized rapid prototyping for real-time embedded heterogeneous multiprocessor,” in Proc.CODES, Rome,Italy,May 1999, CD-ROM.
[29]M.-W.Naouar et al.,IP-Cores Library.[Online].Available:http://www. u-cergy. fr/etud/ufr/composan/iupge/IP_cores/index.htm |