分频程序经synthesis综合后仿真信号没出来

只看该作者 · 2012-10-25 23:30

本帖最后由 yanglei04053175 于 2012-10-25 23:40 编辑

Verilog分频程序：
`timescale 1ns/1ps
module Generator(clk,out);
input clk;
output out;

reg[3:0] num = 4'd1/* synthesis preserve = 1 */;
reg out = 1'b0/* synthesis preserve = 1 */;

always @(posedge clk)
begin
if(num == 4'b0101)
begin
out <= ~out;
num <= 4'b0001;
end
else num <= num + 1'b1;
end
Testbench程序：
`timescale 1ns/1ps
module testbench;
reg clk;
wire out;

initial
begin
clk = 1'b0;
forever
#12.5 clk = ~clk;
end

Generator band_0(
                  .clk(clk),
                  .out(out)
                  );
endmodule

前ModelSim仿真没问题，综合后ModelSim仿真out信号输出为一条红线，大侠帮忙看看，很急啊！