这个系统的一些参数是这样的：SDRAM 时钟100MHZ ，EMIF时钟 100MHZ，设置如下程序的，希望得到前辈们的指点。
把程序代码也贴出来：这是合众达的5502开发板的测试例程，因为在我的程序里SDRAM消耗太多时间，所以单独用这个来测试SDRAM操作速度。
#include <csl.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_chip.h>
#include <csl_emifBhal.h>
#include <stdio.h>
#define GPIODIR (*(volatile ioport Uint16*)(0x3400))
#define GPIODATA (*(volatile ioport Uint16*)(0x3401))
#define DataLength 1000
Uint16 i;
#pragma DATA_SECTION (SourData,".sourdata")
Uint32 SourData[DataLength];
/*SDRAM的EMIF设置*/
EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK( // EMIF Global Control Register 1
EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED, // Hold enable
EMIF_GBLCTL1_EK1HZ_EK1EN, // High-Z control
EMIF_GBLCTL1_EK1EN_ENABLED // ECLKOUT1 Enable
),
EMIF_GBLCTL2_RMK( // EMIF Global Control Register 2
EMIF_GBLCTL2_EK2RATE_4XCLK, // ECLKOUT2 Rate
EMIF_GBLCTL2_EK2HZ_EK2EN, // EK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
EMIF_GBLCTL2_EK2EN_ENABLED // ECLKOUT2 Enable (enabled by default)
),
EMIF_CE1CTL1_RMK( // CE1 Space Control Register 1
EMIF_CE1CTL1_TA_DEFAULT,
EMIF_CE1CTL1_READ_STROBE_DEFAULT,
EMIF_CE1CTL1_MTYPE_DEFAULT,
EMIF_CE1CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE1CTL1_READ_HOLD_DEFAULT
),
EMIF_CE1CTL2_RMK( // CE1 Space Control Register 2
EMIF_CE1CTL2_WRITE_SETUP_DEFAULT,
EMIF_CE1CTL2_WRITE_STROBE_DEFAULT,
EMIF_CE1CTL2_WRITE_HOLD_DEFAULT,
EMIF_CE1CTL2_READ_SETUP_DEFAULT
),
EMIF_CE0CTL1_RMK( // CE0 Space Control Register 1
EMIF_CE0CTL1_TA_DEFAULT,
EMIF_CE0CTL1_READ_STROBE_OF(2),
EMIF_CE0CTL1_MTYPE_32BIT_SBSRAM,
EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE0CTL1_READ_HOLD_OF(2)
),
EMIF_CE0CTL2_RMK( // CE0 Space Control Register 2
EMIF_CE0CTL2_WRITE_SETUP_OF(2),
EMIF_CE0CTL2_WRITE_STROBE_OF(2),
EMIF_CE0CTL2_WRITE_HOLD_OF(2),
EMIF_CE0CTL2_READ_SETUP_OF(2)
),
EMIF_CE2CTL1_RMK( // CE2 Space Control Register 1
EMIF_CE2CTL1_TA_DEFAULT, // Not use for SDRAM (asynchronous memory types only)
EMIF_CE2CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_32BIT_SDRAM, // 32-bit-wide SDRAM
EMIF_CE2CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE2CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE2CTL2_RMK( // CE2 Space Control Register 2
EMIF_CE2CTL2_WRITE_SETUP_OF(5), // Write setup width
EMIF_CE2CTL2_WRITE_STROBE_OF(1), // Write strobe width
EMIF_CE2CTL2_WRITE_HOLD_OF(5), // Write hold width
EMIF_CE2CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_CE3CTL1_RMK( // CE3 Space Control Register 1
EMIF_CE3CTL1_TA_DEFAULT, // Not use for SDRAM (asynchronous memory types only)
EMIF_CE3CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_32BIT_SDRAM, // 32-bit-wide SDRAM
EMIF_CE3CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE3CTL2_RMK( // CE3 Space Control Register 2
EMIF_CE3CTL2_WRITE_SETUP_DEFAULT, // Write setup width
EMIF_CE3CTL2_WRITE_STROBE_DEFAULT, // Write strobe width
EMIF_CE3CTL2_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_SDCTL1_RMK( // SDRAM Control Register 1
EMIF_SDCTL1_TRC_OF(5), // Specifies tRC value of the SDRAM in EMIF clock cycles.
EMIF_SDCTL1_SLFRFR_DISABLED // Auto-refresh mode
),
EMIF_SDCTL2_RMK( // SDRAM Control Register 2
0x11, // 4 banks,11 row address, 8 column address
EMIF_SDCTL2_RFEN_ENABLED, // Refresh enabled
EMIF_SDCTL2_INIT_INIT_SDRAM,
EMIF_SDCTL2_TRCD_OF(1), // Specifies tRCD value of the SDRAM in EMIF clock cycles
EMIF_SDCTL2_TRP_OF(1) // Specifies tRP value of the SDRAM in EMIF clock cycles
),
0x61B, // SDRAM Refresh Control Register 1
0x0100, // SDRAM Refresh Control Register 2
EMIF_SDEXT1_RMK( // SDRAM Extension Register 1
EMIF_SDEXT1_R2WDQM_1CYCLE,
EMIF_SDEXT1_RD2WR_3CYCLES,
EMIF_SDEXT1_RD2DEAC_1CYCLE,
EMIF_SDEXT1_RD2RD_1CYCLE,
EMIF_SDEXT1_THZP_OF(1), // tPROZ2=2
EMIF_SDEXT1_TWR_OF(1), //
EMIF_SDEXT1_TRRD_2CYCLES,
EMIF_SDEXT1_TRAS_OF(4),
EMIF_SDEXT1_TCL_3CYCLES
),
EMIF_SDEXT2_RMK( // SDRAM Extension Register 2
EMIF_SDEXT2_WR2RD_0CYCLES,
EMIF_SDEXT2_WR2DEAC_1CYCLE,
0,
EMIF_SDEXT2_R2WDQM_1CYCLE
),
EMIF_CE1SEC1_DEFAULT, // CE1 Secondary Control Register 1
EMIF_CE0SEC1_DEFAULT, // CE0 Secondary Control Register 1
EMIF_CE2SEC1_DEFAULT, // CE2 Secondary Control Register 1
EMIF_CE3SEC1_DEFAULT, // CE3 Secondary Control Register 1
EMIF_CESCR_DEFAULT // CE Size Control Register
};
main()
{
Uint16 Errcount = 0;
/* 初始化CSL库 */
CSL_init();
/* EMIF为全EMIF接口*/
CHIP_RSET(XBSR,0x0001);
/* 设置系统的运行速度为300MHz */
PLL_setFreq(1, 0xF, 0, 1, 3, 2, 0);
/* 初始化DSP的外部SDRAM */
EMIF_config(&MyEmifConfig);
/* 向SDRAM中写入数据 */
for(i=0;i<DataLength;i++)
{
SourData = i;
}
Errcount = 0;
/* 读出SDRAM中的数据,并判断是否成功 */
for(i=0;i<DataLength;i++)
{
if(i != SourData)
Errcount++;
}
if(Errcount != 0)
printf("SEED_DEC5502 SDRAM 操作失败
");
else
printf("SEED_DEC5502 SDRAM 操作成功
");
GPIODIR=0xff;
while(1)
{
GPIODATA=0x10;
SourData[10]= 0x05; 这个操作用了210ns，太长了
GPIODATA=0x00;
}
} |
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