求教关于状态机！！！

只看该作者 · 2012-11-2 15:01

我现在用的是ISE13.1，我看教程，编写状态机时有个State CAD，可以绘制状态图然后直接生成verilog,我这个怎么找不到呢。

在工程添加文件时，怎么没有教程里的state Diagrm 这个选项

最后个我自己用verilog写了个状态机，请问综合后在ISE上能看到状态转移图吗，我只能看到RTL电路图。

1万 · 2012-11-2 16:00

The State Diagram Editor (StateCAD) has been deprecated in ISE 11.1. Xilinx will no longer be
making bug fixes or enhancements to State Diagram Editor or
upgrading to support new operating systems. As such, the sc.exe delivered in ISE
10.1 is the final version.

Users who desire to use the State Diagram Editor may use it as a standalone
application from an ISE 10.1installation.
From the State Diagram Editor, the user may generate HDL and use it as a source
file in an ISE 11.1 (or any other version) project.