求助高手 想用外部来触发信号使FIFO的RAM（0）=“00000000”
撤掉触发信号RAM（0）=“11111111”
编写的程序如下 请问 哪有问题
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY fifo_2 is
GENERIC(w: integer:=2560;
k: integer:=8);
PORT(wclk,rclk,reset,wr,rd,triger: IN std_logic;
din:IN std_logic_vector(k-1 DOWNTO 0);
dout:OUT std_logic_vector(k-1 DOWNTO 0);
full,empty:OUT std_logic);
END fifo_2;
ARCHITECTURE fifo_arch OF fifo_2 IS
TYPE memory IS ARRAY(0 to w-1) OF std_logic_vector(k-1 DOWNTO 0);
SIGNAL ram:memory;
SIGNAL wp,rp:integer RANGE 0 TO w-1;
SIGNAL in_full,in_empty:std_logic;
BEGIN
fifo_write_data:PROCESS(wclk,triger)
BEGIN
IF rising_edge(wclk)THEN
IF(wr='0' and in_full='0')THEN
ram(wp)<=din;
if (triger='1') then
ram(0)<="00000000";
else
ram(0)<="11111111";
end if;
END IF;
END IF;
END PROCESS fifo_write_data;
fifo_write_pointer:PROCESS(wclk,reset)
BEGIN
IF(reset='1')THEN
wp<=1;
in_full<='0';
in_empty<='1';
ELSIF rising_edge(wclk)then
IF (in_full='0' and wr='0')THEN
in_empty<='0';
IF(wp=w-1)THEN
wp<=1;
in_full<='1';
ELSE wp<=wp+1;
END IF;
END IF;
END IF;
END PROCESS fifo_write_pointer;
fifo_read_pointer:PROCESS(rclk,reset)
BEGIN
IF(reset='1')THEN
rp<=0;
ELSIF rising_edge(rclk)THEN
IF(in_empty='0' and rd='0')THEN
IF(rp=w-1)THEN
rp<=0;
ELSE rp<=rp+1;
END IF;
END IF;
END IF;
END PROCESS fifo_read_pointer;
fifo_read_data:PROCESS(rclk)
BEGIN
IF rising_edge(rclk)THEN
IF(rd='0' and in_empty='0')THEN
dout<=ram(rp);
END IF;
END IF;
END PROCESS fifo_read_data;
full<=in_full;
empty<=in_empty;
END fifo_arch; |
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