新手求教，Verilog 写的抢答器

只看该作者 · 2012-12-12 21:46

本帖最后由 jim727 于 2012-12-13 21:35 编辑

小弟新手，很多不懂，谢谢各位帮助

我用quartus 9.1做的，我想知道，为什么变成未知值（X）了
代码很乱，请不惜赐教

我这个是做抢答器，EN1~6是抢答按钮，GRP1~6是各组得分（初始化10分），UP是开始和重置信号，DN是高位得分，低位扣分，check是确认评分。over是控制1次抢答只能评分一次，en是看是否有人按下抢答按钮。lock是控制让第一组抢答后屏蔽其他组信号。我扬声器没写，所以留下记号。
---------------------------eda8_8.v-----------------------------------------------------------------
module eda8_8(CLK,en1,en2,en3,en4,en5,en6,GRP1,GRP2,GRP3,GRP4,GRP5,GRP6,UP,DN,check);
input UP,DN,en1,en2,en3,en4,en5,en6,CLK,check;
output  [7:0] GRP1,GRP2,GRP3,GRP4,GRP5,GRP6;
reg [7:0] GRP1,GRP2,GRP3,GRP4,GRP5,GRP6;
reg EN1,EN2,EN3,EN4,EN5,EN6,lock,checked,over;
wire en;
initial
begin
lock<=1'b1;
GRP1<=7'b00010000;
GRP2<=7'b00010000;
GRP3<=7'b00010000;
GRP4<=7'b00010000;
GRP5<=7'b00010000;
GRP6<=7'b00010000;
checked<=1'b0;
over<=1'b1;
end
always @(check or GRP1 or GRP2 or GRP3 or GRP4 or GRP5 or GRP6 )
begin
if(check);
else
over=~over;
end
always @(posedge CLK)
begin
case({UP,DN})
2'b10://wrong answer
begin
if(checked&over)
begin
case({EN1,EN2,EN3,EN4,EN5,EN6})
6'b100000:
begin
      if(GRP1[3:0]!=4'h0)
      GRP1[3:0]<=GRP1[3:0]-4'h1;
else
      begin
      GRP1[7:4]<=GRP1[7:4]-4'h1;
      GRP1[3:0]<=4'h9;
      end
end
6'b010000:
begin
      if(GRP2[3:0]!=4'h0)
      GRP2[3:0]<=GRP2[3:0]-4'h1;
else
      begin
      GRP2[7:4]<=GRP2[7:4]-4'h1;
      GRP2[3:0]<=4'h9;
      end
end
6'b001000:
begin
      if(GRP3[3:0]!=0)
      GRP3[3:0]<=GRP3[3:0]-4'h1;
else
      begin
      GRP3[7:4]<=GRP3[7:4]-4'h1;
      GRP3[3:0]<=4'h9;
      end
end
6'b000100:
begin
      if(GRP4[3:0]!=0)
      GRP4[3:0]<=GRP4[3:0]-4'h1;
else
      begin
      GRP4[7:4]<=GRP4[7:4]-4'h1;
      GRP4[3:0]<=4'h9;
      end
end
6'b000010:
begin
      if(GRP5[3:0]!=0)
      GRP5[3:0]<=GRP5[3:0]-4'h1;
else
      begin
      GRP5[7:4]<=GRP5[7:4]-4'h1;
      GRP5[3:0]<=4'h9;
      end
end
6'b000001:
begin
      if(GRP6[3:0]!=0)
      GRP6[3:0]<=GRP6[3:0]-4'h1;
else
      begin
      GRP6[7:4]<=GRP6[7:4]-4'h1;
      GRP6[3:0]<=4'h9;
      end
end
default:
begin
GRP1 <= GRP1;GRP2 <= GRP2;
GRP3 <= GRP3;GRP4 <= GRP4;
GRP5 <= GRP5;GRP6 <= GRP6;
end
endcase
//bi~~~~~~~~~~~~500+2000hz
end
end
2'b11:///right answer
begin
if(checked&over)
begin
case({EN1,EN2,EN3,EN4,EN5,EN6})
6'b100000:
begin
      if(GRP1[3:0]==4'h9)
      begin
      GRP1[7:4]<=GRP1[7:4]+4'h1;
      GRP1[3:0]<=4'h0;
      end
else
      begin
      GRP1[3:0]<= GRP1[3:0]+4'h1;
      end
end
6'b010000:
begin
      if(GRP2[3:0]==9)
      begin
      GRP2[7:4]<=GRP2[7:4]+4'h1;
      GRP2[3:0]<=4'h0;
      end
else
      begin
      GRP2[3:0]<=GRP2[3:0]+4'h1;
      end
end
6'b001000:
begin
      if(GRP3[3:0]==9)
      begin
      GRP3[7:4]<=GRP3[7:4]+4'h1;
      GRP3[3:0]<=4'h0;
      end
else
      begin
      GRP3[3:0]<=GRP3[3:0]+4'h1;
      end
end
6'b000100:
begin
      if(GRP4[3:0]==9)
      begin
      GRP4[7:4]<=GRP4[7:4]+4'h1;
      GRP4[3:0]<=4'h0;
      end
else
      begin
      GRP4[3:0]<=GRP4[3:0]+4'h1;
      end
end
6'b000010:
begin
      if(GRP5[3:0]==4'h9)
      begin
      GRP5[7:4]<=GRP5[7:4]+4'h1;
      GRP5[3:0]<=4'h0;
      end
else
      begin
      GRP5[3:0]<=GRP5[3:0]+4'h1;
      end
end
6'b000001:
begin
      if(GRP6[3:0]==9)
      begin
      GRP6[7:4]<=GRP6[7:4]+4'h1;
      GRP6[3:0]<=4'h0;
      end
else
      begin
      GRP6[3:0]<=GRP6[3:0]+4'h1;
      end
end
default:
begin
GRP1 <= GRP1;GRP2 <= GRP2;
GRP3 <= GRP3;GRP4 <= GRP4;
GRP5 <= GRP5;GRP6 <= GRP6;
end
endcase
//bi~~~~~~~~~~~~500+1000hz
end
   end
2'b00://not start yet
begin
if(EN1|EN2|EN3|EN4|EN5|EN6);
//bi~~~~~~~~~~~~500hz
end
2'b01://not start yet
begin
end
endcase

end
assign en=en1|en2|en3|en4|en5|en6;
always @(posedge en or negedge UP or posedge check)
begin
if(check)checked=check;
case({en1,en2,en3,en4,en5,en6})
6'b100000:
begin
EN1=1'b1&lock;
end
6'b010000:
begin
EN2=1'b1&lock;
end
6'b001000:
begin
EN3=1'b1&lock;
end
6'b000100:
begin
EN4=1'b1&lock;
end
6'b000010:
begin
EN5=1'b1&lock;
end
6'b000001:
begin
EN6=1'b1&lock;
end
default:
begin end
endcase
if(!UP)
begin
checked=1'b0;
lock=~lock;
EN1=1'b0; EN2=1'b0;
EN3=1'b0; EN4=1'b0;
EN5=1'b0; EN6=1'b0;
end
end
endmodule