本帖最后由 worlfx 于 2012-12-24 11:27 编辑
save and check没有报错，
芯片：EPM7128SLC-84 ALE-15 RD-22 WR-23....
引脚配置后save and compile报错
报错信息：
Error: lllegal assignment - global clock "ALE" on pin 15
Error: output enable signal can't be driven by pin "RD"
info: no fit possible with the currnet device
error: no fit found,generating report file
module mcu_wr(MCU_DATA,RD,WR,ALE,PORT1_KEY,PORT2_LED);
inout[7:0] MCU_DATA;
input RD;
input WR;
input ALE;
input[7:0] PORT1_KEY;
output[7:0] PORT2_LED;
//----------------------------------
reg[7:0] ADDRESS_REG;
reg[7:0] PORT1_KEY_REG;
reg[7:0] PORT2_LED_REG;
//-----------------------------------
always@(negedge ALE)
begin
ADDRESS_REG=MCU_DATA;
end
always@(negedge RD)
begin
if(ADDRESS_REG==8'b00000000)PORT1_KEY_REG= PORT1_KEY;
else PORT1_KEY_REG=8'bzzzzzzzz;
end
//-----------------------------------
always@(negedge WR)
begin
if(ADDRESS_REG==8'b00000001)PORT2_LED_REG=MCU_DATA;
end
//-----------------------------------
assign MCU_DATA=RD? 8'bzzzzzzzz: PORT1_KEY_REG;
assign PORT2_LED=PORT2_LED_REG;
//-----------------------------------
endmodule
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