MCBSP2 外接ALC5621 codec IC，
MCBSP2_CLKX 1.536M，MCBSP2_FSX 48K，以下是相关寄存器 配置。
MCBSPLP_PCR_REG配置成下降沿发送数据，
CLKXP Transmit Clock Polarity RW 0x0
0x0: Transmit data driven on rising edge of CLKX
0x1: Transmit data driven on falling edge of CLKX
但是在测量数据输出时MCBSP2_DX确不是48K，我有哪里没有配置正确吗？请大家分析一下。
regs->spcr2=0x00000230
regs->spcr1=0x00000030
regs->rcr2=0x00000040
regs->rcr1=0x00000140
regs->xcr2=0x00000040
regs->xcr1=0x00000140
regs->srgr2=0x0000001f
regs->srgr1=0x00000000
regs->mcr2=0x00000000
regs->mcr1=0x00000000
regs->pcr0=0x00000003
regs->rcerc=0x00000000
regs->rcerd=0x00000000
regs->xcerc=0x00000000
regs->xcerd=0x00000000
regs->rcere=0x00000000
regs->rcerf=0x00000000
regs->xcerf=0x00000000
regs->rcerg=0x00000000
regs->rcerh=0x00000000
regs->xcerg=0x00000000
regs->xcerh=0x00000000
regs->xccr=0x00001009
regs->rccr=0x00000809 |
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