昏迷,你们遇到这么诡异问题吗??

发表于 2013-1-8 16:27

本帖最后由 yyql008 于 2013-1-8 16:28 编辑

  STM32107B单片机,我用了MDK4.22,还有IAR 5.5.
其中单片机复位后,会调用SetSysClockTo72() 函数
static void SetSysClockTo72(void)
{
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  /* Enable HSE */
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
HSEStatus = (uint32_t)0x01;

  }
  else
  {
HSEStatus = (uint32_t)0x00;

  }

  if (HSEStatus == (uint32_t)0x01)
  {
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;

/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;

/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */

RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                           RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                           RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}

/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
                        RCC_CFGR_PLLMULL9);
#else
/*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
                                    RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */

/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}

/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock
      configuration. User can add here some code to deal with this error */
  }
}
诡异的是在MDK 最先执行的是RCC->CR |= ((uint32_t)RCC_CR_HSEON);
点单步,程序向上跑了!!!!执行 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
这个函数后的程序也跑乱了,经常从下面往上面跑.有时这两句 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
HSEStatus = (uint32_t)0x01;

  }
  else
  {
HSEStatus = (uint32_t)0x00;

  }
一个都不进入!!!
在IAR 中会执行
else
  {
HSEStatus = (uint32_t)0x00;
  }
然后后面的条件if (HSEStatus == (uint32_t)0x01)会满足!!!
我在HSEStatus = (uint32_t)0x00;后面加了一个全局变量Test = 0;
会执行Test = 0;这一句.
不过在仿真器中观察到Test 还是等于1.

在里面写全局变量调试都不行(视乎这里内存还未初始化),不过也不会这样诡异.我两个编译器单片机选型都是正确的.

发表于 2013-1-8 16:32

发表于 2013-1-8 16:35

但是后面的程序都是正确的,就那个函数有那个问题!!!!
很怀疑你们也可能有这个问题.只有是STM32单片机都试试吧.

发表于 2013-1-8 21:17

1.工程设置改为调试时不优化

2.

复制

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)//此处加断点观察StartupCounter变量值和HSEStatus值，也有可能你在这里无法加断点

  {

    HSEStatus = (uint32_t)0x01;



  }

  else

  {

    HSEStatus = (uint32_t)0x00;



  }

做完上面的再回来沟通一下

发表于 2013-1-18 13:30

回楼上,那天也把优化等级设为最低的,
但MDK,一直运行不正常.我的MDK是4.22的.
现在用IAR,一看到MDK就头大,想起以前用的keil,实在不喜欢这编译器

发表于 2013-1-18 15:34

昏迷,你们遇到这么诡异问题吗??

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