本帖最后由 wolftc 于 2013-1-22 10:12 编辑
Backkom80 发表于 2013-1-22 08:12 
1，时钟的输入需从专用的时钟引脚输入，这些专用IO联接着FPGA内部的全局缓冲网络。对于输出时钟比较灵活 ...
Spartan-6系列输出时钟，不加ODDR2会出错。
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.
< PIN "RGB_GEN_T/clks/U1/pllx2_dcm/clkout1_buf.O" CLOCK_DEDICATED_ROUTE =
FALSE; >错误信息里所说的:在SPARTAN6的设计中，由时钟管理IP分出来的时钟线是不能直连到一些FPGA引脚的，如错误信息中所说，你需要采用一个ODDR2的模块。该模块是一个IO BUFFER，你将ODDR的D0连到高电平，将D1连到低电平，将时钟连到C0，将时钟取反连到C1然后将ODDR的输出再连到FPGA的引脚上去。so,在低端器件中，需要例化一个ODDR。
附加一个问题：要求输出时钟clkx1,输出数据data速率为clkx2(2倍clkx1)。我的做法是，同一个PLL产生clkx1,clkx2，以保证clkx1,clkx2同相位。前面都是clkx1处理的数据，到输出模块时，用clkx2将原一个数据分2次输出。这就产生异步时钟问题，导致data的建立保持时间不够，时序报警告。
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