时序报告的不明白之处

只看该作者 · 2013-1-22 20:22

   最近在学习约束的一些东西，有些不明白的地方，想请教各位：

   写的简单的串并转换代码：

   module shift #(parameter DATIN_WIDTH = 16,
            parameter DATO_WIDTH  = 16)
            (
               input  clk,
               input  rst_,
               input  ld,
               input [DATIN_WIDTH-1:0] data_in,
               input  shift_in,
               input  shift_en,
               output shift_out,
               output reg [DATO_WIDTH-1:0] data_out);


               always @(posedge clk or negedge rst_)
               begin
                        if(!rst_)
                              data_out<= 'b0;
                     else if(ld)
                           data_out <= data_in;
                     else if(shift_en)
                           data_out<= {data_out[DATO_WIDTH-2:0],shift_in};
               end

               assign shift_out = data_out[DATO_WIDTH-1];
   endmodule

   在synplify9.6.2中的作了简单约束，其中.sdc文件所作的约束内容：

      define_input_delay -disable    -default -improve 0.00 -route 0.00
      define_output_delay -disable    -default -improve 0.00 -route 0.00
      define_input_delay             {rst_}  1.00 -improve 0.00 -route 0.00
      define_input_delay             {ld}  1.00 -improve 0.00 -route 0.00
      define_input_delay             {data_in[15:0]}  1.00 -improve 0.00 -route 0.00
      define_input_delay             {shift_in}  1.00 -improve 0.00 -route 0.00
      define_input_delay             {shift_en}  1.00 -improve 0.00 -route 0.00
      define_output_delay             {shift_out}  2.00 -improve 0.00 -route 0.00
      define_output_delay             {data_out[15:0]}  2.00 -improve 0.00 -route 0.00

      时钟在 implementation options 中约束在100MHz。

最后在时序分析报告察看：

      Input Ports:

            Port          Starting          User          Arrival    Required
         Name          Reference    Constraint    Time       Time       Slack
                                 Clock
----------------------------------------------------------------------------------
   data_in[0]    System (rising)    1.000       1.000    11.671    10.671
   data_in[1]    System (rising)    1.000       1.000    11.671    10.671
         .
         .
         ld             System (rising)    1.000       1.000    10.310    9.310
      rst_          System (rising)    1.000       NA       NA          NA
      shift_en       System (rising)    1.000       1.000    10.694    9.694
      shift_in       System (rising)    1.000       1.000    11.671    10.671
=======================================================

   Output Ports:

            Port                Starting          User       Arrival    Required
         Name             Reference       Constraint    Time       Time       Slack
                                 Clock
-------------------------------------------------------------------------------------
      data_out[0]    shift|clk (rising)    2.000       6.961    8.000       1.039
      data_out[1]    shift|clk (rising)    2.000       6.961    8.000       1.039
            .
            .
      data_out[15]    shift|clk (rising)    2.000       6.961    8.000       1.039
         shift_out       shift|clk (rising)    2.000       6.961    8.000       1.039
=======================================================

请问，代码中只有一个时钟clk，为什么会在输入的里面时钟那一项是system，而且后面详细的报告也有：

      ====================================
         Detailed Report for Clock: shift|clk
      ====================================

      。。。

      ====================================
         Detailed Report for Clock: System
      ====================================

      。。。

两个报告。这两个报告有什么关系，这个system该如何理解？