本帖最后由 pocker5200 于 2013-1-25 23:11 编辑
警告错误信息如下，红字部分我很无语……
贴上我在UCF文件里的约束，芯片是xc6slx25-2ftg256。
bank0只是连接一个PHY，总共10输入，5个输出，按理说默认约束也不会超出SSO范围。
手册翻了半天也不知道问题出在哪，约束文件明明写的电平标准是LVCMOS33,不知道这个LVCMOS25是怎么出现的，整个系统根本就没2.5V。
特来求助了，第一次遇到这样的问题，ISE13.4，谢谢.
PS:最新补充……
map report 节选
IO Utilization:
Number of bonded IOBs: 56 out of 186 30%
Number of LOCed IOBs: 53 out of 56 94%
IOB Flip Flops: 26
IOBs占用了非常多，似乎和下面的警告有关联，FT256封装的用户IO有186个，但是我的整个设计只用了56个管脚……
难道那最后3个管脚没办法布了么。
-----------------------------------------------------------------------------------------------------------------------
CONFIG VCCAUX = "3.3" ;
Net Ethernet_MAC_1_PHY_tx_data_pin<0> LOC = C6 | IOSTANDARD = LVCMOS33 | DRIVE = 8;
Net Ethernet_MAC_1_PHY_rx_data_pin<1> LOC = A5 | IOSTANDARD = LVCMOS33 | DRIVE = 8;
Net Ethernet_MAC_1_PHY_rx_data_pin<2> LOC = B5 | IOSTANDARD = LVCMOS33 | DRIVE = 8;
Net Ethernet_MAC_1_PHY_rx_data_pin<3> LOC = C5 | IOSTANDARD = LVCMOS33 | DRIVE = 8;
---------------------------------------------------------------------------------------------
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: Ethernet_MAC_1_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33
Comp: Ethernet_MAC_1_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS25
Comp: Ethernet_MAC_1_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS25
Comp: Ethernet_MAC_1_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS25
INFO:Place:834 - Only a subset of IOs are locked. Out of 56 IOs, 53 are locked
and 3 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = 12
Ethernet_MAC_1_PHY_tx_data_pin<1>
Ethernet_MAC_1_PHY_tx_data_pin<2>
Ethernet_MAC_1_PHY_tx_data_pin<3>
This may be due to either an insufficient number of sites available on the
device, too many prohibited sites,
or incompatible I/O Standards locked or range constrained to I/O Banks with
valid sites.
This situation could possibly be resolved by one (or all) of the
following actions:
a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by
using LOC or range constraints.
b) Maximizing available I/O Banks resources for special IOBs by choosing
lower capacity I/O Banks if possible.
c) If applicable, decreasing the number of user prohibited sites or using a
larger device.
Phase 2.7 Design Feasibility Check (Checksum:3c918686) REAL time: 50 secs
Total REAL time to Placer completion: 50 secs
Total CPU time to Placer completion: 49 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
|
楼主
标题置顶
标题高亮
